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PIC12F683 Data Sheet
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
* 8-bit, 8-pin Devices Protected by Microchip's Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.
2004 Microchip Technology Inc.
Preliminary
DS41211B
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart and rfPIC are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartShunt and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
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Preliminary
2004 Microchip Technology Inc.
PIC12F683
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
High-Performance RISC CPU
* Only 35 instructions to learn: - All single-cycle instructions except branches * Operating speed: - DC - 20 MHz oscillator/clock input - DC - 200 ns instruction cycle * Interrupt capability * 8-level deep hardware stack * Direct, Indirect and Relative Addressing modes
Low-Power Features
* Standby Current: - 1 nA @ 2.0V, typical * Operating Current: - 8.5 A @ 32 kHz, 2.0V, typical - 100 A @ 1 MHz, 2.0V, typical * Watchdog Timer Current: - 1 A @ 2.0V, typical
Peripheral Features Special Microcontroller Features
* Precision Internal Oscillator: - Factory calibrated to 1% - Software selectable frequency range of 8 MHz to 31 kHz - Two-speed Start-up mode - Crystal fail detect for critical applications - Clock mode switching during operation for power savings * Power-saving Sleep mode * Wide operating voltage range. (2.0V-5.5V) * Industrial and Extended temperature range * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Multiplexed Master Clear with pull-up/input pin * Programmable code protection * High Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM Retention: > 40 years * 6 I/O pins with individual direction control: - High current source/sink for direct LED drive - Interrupt-on-pin change - Individually programmable weak pull-ups - Ultra Low-Power Wake-up on GP0 * Analog comparator module with: - One analog comparator - Programmable on-chip voltage reference (CVREF) module (% of VDD) - Comparator inputs and output externally accessible * A/D Converter: - 10-bit resolution and 4 channels * Timer0: 8-bit timer/counter with 8-bit programmable prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Capture, Compare, PWM module: - 16-bit Capture, max resolution 12.5 ns - Compare, max resolution 200 ns - 10-bit PWM, max frequency 20 kHz * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins
Timers 8/16-bit 2/1
Program Memory Device Flash (words) PIC12F683 2048
Data Memory I/O SRAM (bytes) 128 EEPROM (bytes) 256 6 4 1 10-bit A/D (ch) Comparators
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 1
PIC12F683
Pin Diagram
8-pin PDIP, SOIC, DFN-S
VDD GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/VPP
1
8
VSS GP0/AN0/CIN+/ICSPDAT/ULPWU GP1/AN1/CIN-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1
PIC12F683
2 3 4
7 6 5
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PIC12F683
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 7 3.0 Clock Sources ............................................................................................................................................................................ 19 4.0 GPIO Port................................................................................................................................................................................... 31 5.0 Timer0 Module ........................................................................................................................................................................... 39 6.0 Timer1 Module with Gate Control............................................................................................................................................... 41 7.0 Timer2 Module ........................................................................................................................................................................... 45 8.0 Comparator Module.................................................................................................................................................................... 47 9.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 55 10.0 Data EEPROM Memory ............................................................................................................................................................. 65 11.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 69 12.0 Special Features of the CPU...................................................................................................................................................... 75 13.0 Instruction Set Summary ............................................................................................................................................................ 95 14.0 Development Support............................................................................................................................................................... 103 15.0 Electrical Specifications............................................................................................................................................................ 109 16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 131 17.0 Packaging Information.............................................................................................................................................................. 133 Appendix A: Data Sheet Revision History.......................................................................................................................................... 137 Appendix B: Migrating From Other PICmicro(R) Devices .................................................................................................................... 137 Index .................................................................................................................................................................................................. 139 On-line Support .................................................................................................................................................................................. 143 Systems Information and Upgrade Hot Line ...................................................................................................................................... 143 Reader Response .............................................................................................................................................................................. 144 Product Identification System ............................................................................................................................................................ 145
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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2004 Microchip Technology Inc.
Preliminary
DS41211B-page 3
PIC12F683
NOTES:
DS41211B-page 4
Preliminary
2004 Microchip Technology Inc.
PIC12F683
1.0 DEVICE OVERVIEW
This document contains device specific information for the PIC12F683. Additional information may be found in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The reference manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC12F683 is covered by this data sheet. It is available in 8-pin PDIP, SOIC and DFN-S packages. Figure 1-1 shows a block diagram of the PIC12F683 device. Table 1-1 shows the pinout description.
FIGURE 1-1:
PIC12F683 BLOCK DIAGRAM
INT Configuration 13 Program Counter Flash 2k x 14 Program Memory Data Bus 8 GP0 GP1 8-Level Stack (13-bit) RAM 128 bytes File Registers RAM Addr 9 Addr MUX Direct Addr 7 Indirect Addr GP2 GP3 GP4 GP5
Program Bus
14 Instruction reg
8
FSR reg Status reg 8
3 Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Detect Internal Oscillator Block 8 W reg
MUX
ALU
OSC1/CLKIN OSC2/CLKOUT
Timing Generation
CCP1 T1G T1CKI Timer0 T0CKI Timer1 Timer2 CCP MCLR VDD VSS
Analog-to-Digital Converter
1 Analog Comparator and Reference 8
EEDATA 256 bytes Data EEPROM EEADDR
VREF
AN0 AN1 AN2 AN3
CIN-
CIN+
COUT
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Preliminary
DS41211B-page 5
PIC12F683
TABLE 1-1: PIC12F683 PINOUT DESCRIPTION
Name VDD GP5/T1CKI/OSC1/CLKIN Function VDD GP5 T1CKI OSC1 CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP4 AN3 T1G OSC2 CLKOUT GP3/MCLR/VPP GP3 MCLR VPP GP2/AN2/T0CKI/INT/COUT/CCP1 GP2 AN2 T0CKI INT COUT CCP1 GP1/AN1/CIN-/VREF/ICSPCLK GP1 AN1 CINVREF ICSPCLK GP0/AN0/CIN+/ICSPDAT/ULPWU GP0 AN0 CIN+ ICSPDAT ULPWU VSS Legend: VSS AN = Analog input or output TTL = TTL compatible input HV = High Voltage Input Type Power TTL ST XTAL ST TTL AN ST -- -- TTL ST HV ST AN ST ST -- ST TTL AN AN AN ST TTL AN AN ST AN Power Output Type -- CMOS -- -- -- CMOS -- -- XTAL CMOS -- -- -- CMOS -- -- -- CMOS CMOS CMOS -- -- -- -- CMOS -- -- CMOS -- -- Positive supply GPIO I/O w/programmable pull-up and interrupt-on-change Timer1 clock Crystal/Resonator External clock input/RC oscillator connection GPIO I/O w/programmable pull-up and interrupt-on-change A/D Channel 3 input Timer1 gate Crystal/Resonator FOSC/4 output GPIO input with interrupt-on-change Master Clear w/internal pull-up Programming voltage GPIO I/O w/programmable pull-up and interrupt-on-change A/D Channel 2 input Timer0 clock input External Interrupt Comparator 1 output Capture input/Compare output/PWM output GPIO I/O w/programmable pull-up and interrupt-on-change A/D Channel 1 input Comparator 1 input External Voltage Reference for A/D Serial Programming Clock GPIO I/O w/programmable pull-up and interrupt-on-change A/D Channel 0 input Comparator 1 input Serial Programming Data I/O Ultra Low-power Wake-up input Ground reference Description
CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal
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2004 Microchip Technology Inc.
PIC12F683
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
2.2
Data Memory Organization
The PIC12F683 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. Only the first 2k x 14 (0000h-07FFh) for the PIC12F683 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 2k x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are general purpose registers, implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns `0' when read. RP0 (Status<5>) is the bank select bit. * RP0 = 0: Bank 0 is selected * RP0 = 1: Bank 1 is selected Note: The IRP and RP1 bits (Status<7:6>) are reserved and should always be maintained as `0's.
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC12F683
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
2.2.1
Stack Level 1 Stack Level 2
GENERAL PURPOSE REGISTER FILE
Stack Level 8 Reset Vector
The register file is organized as 128 x 8 in the PIC12F683. Each register is accessed, either directly or indirectly, through the File Select Register FSR (see Section 2.4 "Indirect Addressing, INDF and FSR Registers").
000h
Interrupt Vector
0004 0005
On-chip Program Memory 07FFh 0800h
1FFFh
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 7
PIC12F683
2.2.2 SPECIAL FUNCTION REGISTERS FIGURE 2-2:
The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
DATA MEMORY MAP OF THE PIC12F683
File Address File Address Indirect addr.(1) OPTION_REG PCL STATUS FSR TRISIO 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h PCLATH INTCON PIE1 PCON OSCCON OSCTUNE PR2 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h WPU IOC 95h 96h 97h 98h VRCON EEDAT EEADR EECON1 EECON2(1) ADRESL ANSEL General Purpose Registers 32 Bytes 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
Indirect addr.(1) TMR0 PCL STATUS FSR GPIO
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h
PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON
0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h
WDTCON CMCON0 CMCON1
18h 19h 1Ah 1Bh 1Ch 1Dh
ADRESH ADCON0
1Eh 1Fh 20h
General Purpose Registers 96 Bytes
BFh
Accesses 70h-7Fh 7Fh BANK 0 BANK 1
F0h FFh
Unimplemented data memory locations, read as `0'. Note 1: Not a physical register.
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PIC12F683
TABLE 2-1:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh INDF TMR0 PCL STATUS FSR GPIO -- -- -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON -- -- WDTCON CMCON0 CMCON1 -- -- -- ADRESH ADCON0 Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 83 Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP(1) -- RP1(1) -- RP0 GP5 TO GP4 PD GP3 Z GP2 DC GP1 C GP0 Indirect Data Memory Address Pointer Unimplemented Unimplemented Unimplemented Unimplemented -- GIE EEIF -- PEIE ADIF -- T0IE CCP1IF Write Buffer for upper 5 bits of Program Counter INTE -- GPIE CMIF T0IF OSFIF INTF TMR2IF GPIF xxxx xxxx 39, 83 0000 0000 17, 83 0001 1xxx 11, 83 xxxx xxxx 17, 83 --xx xxxx 31, 83 -- -- -- -- -- -- -- -- Name
PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD Page
---0 0000 17, 83 0000 0000 13, 83 -- --
TMR1IF 000- 0000 15, 83 xxxx xxxx 41, 83 xxxx xxxx 41, 83
Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Holding Register for the Most Significant Byte of the 16-bit TMR1 T1GINV -- TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS Timer2 Module Register Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte -- -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 Unimplemented Unimplemented -- -- -- -- COUT -- -- -- -- WDTPS3 CINV -- WDTPS2 CIS -- WDTPS1 CM2 -- WDTPS0 CM1 T1GSS CM0
TMR1ON 0000 0000 43, 83 0000 0000 45, 83 xxxx xxxx 70, 83 xxxx xxxx 70, 83 CCP1M0 --00 0000 69, 83 -- -- -- --
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 45, 83
SWDTEN ---0 1000 90, 83 -0-0 0000 47, 83 -- -- -- -- -- -- CMSYNC ---- --10 50, 83
Unimplemented Unimplemented Unimplemented Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result ADFM VCFG -- -- CHS1 CHS0 GO/DONE ADON
xxxx xxxx 57,83 00-- 0000 58,83
Legend: Note 1:
-- = unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented IRP and RP1 bits are reserved, always maintain these bits clear.
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DS41211B-page 9
PIC12F683
TABLE 2-2:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh IOC -- -- VRCON EEDAT EEADR PR2 -- -- WPU(3) INDF OPTION_REG PCL STATUS FSR TRISIO -- -- -- -- PCLATH INTCON -- PCON OSCCON OSCTUNE -- Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 83 GPPU IRP(1) -- INTEDG RP1(1) -- T0CS RP0 TRISIO5 T0SE TO TRISIO4 PSA PD TRISIO3 PS2 Z TRISIO2 PS1 DC TRISIO1 PS0 C 1111 1111 12, 83 0000 0000 17, 83 0001 1xxx 11, 83 xxxx xxxx 17, 83 TRISIO0 --11 1111 32, 83 -- -- -- -- -- T0IE CCP1IE Write Buffer for upper 5 bits of Program Counter INTE -- GPIE CMIE -- OSTS(2) TUN3 T0IF OSFIE -- HTS TUN2 INTF TMR2IE POR LTS TUN1 GPIF -- -- -- -- Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented Unimplemented Unimplemented Unimplemented -- GIE EEIE -- -- -- -- PEIE ADIE -- IRCF2 -- Name
PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD Page
---0 0000 17, 83 0000 0000 13, 83 -- --
8Ch PIE1
TMR1IE 000- 0000 14, 83 BOD SCS TUN0 --01 --qq 16, 83 -110 x000 28, 83 ---0 0000 23, 83 -- -- -- -- -- -- 1111 1111 45, 83
Unimplemented ULPWUE SBODEN IRCF1 -- IRCF0 TUN4
Unimplemented Timer2 Module Period Register Unimplemented Unimplemented -- -- -- -- WPU5 IOC5 WPU4 IOC4 -- IOC3 WPU2 IOC2 WPU1 IOC1 WPU0 IOC0
--11 -111 32, 83 --00 0000 33, 83 -- -- -- --
Unimplemented Unimplemented VREN EEDAT7 EEADR7 -- -- EEDAT6 EEADR6 -- VRR EEDAT5 EEADR5 -- -- EEDAT4 EEADR4 -- VR3 EEDAT3 EEADR3 WRERR VR2 EEDAT2 EEADR2 WREN VR1 EEDAT1 EEADR1 WR VR0
0-0- 0000 53, 83
EEDAT0 0000 0000 65, 83 EEADR0 0000 0000 65, 83 RD ---- x000 66, 84 ---- ---- 66, 84 xxxx xxxx 57, 84 ANS0 -000 1111 59, 84
9Ch EECON1 9Dh EECON2 9Eh 9Fh ADRESL ANSEL
EEPROM Control Register 2 (not a physical register) Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result -- ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1
Legend: Note 1: 2: 3:
-- = unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented IRP and RP1 bits are reserved, always maintain these bits clear. OSCCON bit reset to `0' with Dual Speed Start-up and LP, HS or XT selected as the oscillator. GP3 pull-up is enabled when MCLRE is `1' in the Configuration Word register.
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PIC12F683
2.2.2.1 Status Register
The Status register, shown in Register 2-1, contains: * Arithmetic status of the ALU * Reset status * Bank select bits for data memory (SRAM) The Status register can be the destination for any instruction, like any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the Status register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Status register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see the "Instruction Set Summary". Note 1: Bits IRP and RP1 (Status<7:6>) are not used by the PIC12F683 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS - STATUS REGISTER (ADDRESS: 03h OR 83h)
Reserved Reserved IRP bit 7 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7 bit 6 bit 5
IRP: This bit is reserved and should be maintained as `0' RP1: This bit is reserved and should be maintained as `0' RP0: Register Bank Select bit (used for direct addressing) 1 = Bank 1 (80h-FFh) 0 = Bank 0 (00h-7Fh) TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) For borrow, the polarity is reversed. 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 4
bit 3
bit 2
bit 1
bit 0
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Preliminary
DS41211B-page 11
PIC12F683
2.2.2.2 Option Register
Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to `1' (Option<3>). See Section 5.4 "Prescaler". The Option register is a readable and writable register, which contains various control bits to configure: * * * * TMR0/WDT prescaler External GP2/INT interrupt TMR0 Weak pull-ups on GPIO
REGISTER 2-2:
OPTION_REG - OPTION REGISTER (ADDRESS: 81h)
R/W-1 GPPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual port latch values in WPU register INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on GP2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate(1) 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1: A dedicated 16-bit WDT postscaler is available for the PIC12F683. See Section 12.6 "Watchdog Timer (WDT)" for more information. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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PIC12F683
2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, GPIO change and external GP2/INT pin interrupts.
REGISTER 2-3:
INTCON - INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 GPIE R/W-0 T0IF R/W-0 INTF R/W-0 GPIF bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: GP2/INT External Interrupt Enable bit 1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt GPIE: GPIO Change Interrupt Enable bit(1) 1 = Enables the GPIO change interrupt 0 = Disables the GPIO change interrupt T0IF: TMR0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: GP2/INT External Interrupt Flag bit 1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur GPIF: GPIO Change Interrupt Flag bit 1 = When at least one of the GPIO<5:0> pins changed state (must be cleared in software) 0 = None of the GPIO<5:0> pins have changed state Note 1: IOC register must also be enabled. 2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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Preliminary
DS41211B-page 13
PIC12F683
2.2.2.4 PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 2-4.
REGISTER 2-4:
PIE1 - PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0 EEIE bit 7 R/W-0 ADIE R/W-0 CCP1IE U-0 -- R/W-0 CMIE R/W-0 OSFIE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt Unimplemented: Read as `0' CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the oscillator fail interrupt 0 = disables the oscillator fail interrupt TMR2IE: Timer 2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer 2 to PR2 match interrupt 0 = Disables the Timer 2 to PR2 match interrupt TMR1IE: Timer 1 Overflow Interrupt Enable bit 1 = Enables the Timer 1 overflow interrupt 0 = Disables the Timer 1 overflow interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
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Preliminary
2004 Microchip Technology Inc.
PIC12F683
2.2.2.5 PIR1 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.
REGISTER 2-5:
PIR1 - PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)
R/W-0 EEIF bit 7 R/W-0 ADIF R/W-0 CCP1IF U-0 -- R/W-0 CMIF R/W-0 OSFIF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started ADIF: A/D Interrupt Flag bit 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. Unimplemented: Read as `0' CMIF: Comparator Interrupt Flag bit 1 = Comparator 1 output has changed (must be cleared in software) 0 = Comparator 1 output has not changed OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating TMR2IF: Timer 2 to PR2 Match Interrupt Flag bit 1 = Timer 2 to PR2 match occurred (must be cleared in software) 0 = Timer 2 to PR2 match has not occurred TMR1IF: Timer 1 Overflow Interrupt Flag bit 1 = Timer 1 register overflowed (must be cleared in software) 0 = Timer 1 has not overflowed Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 15
PIC12F683
2.2.2.6 PCON Register
The Power Control (PCON) register contains flag bits (see Table 12-2) to differentiate between a: * * * * Power-on Reset (POR) Brown-out Detect (BOD) Watchdog Timer Reset (WDT) External MCLR Reset
The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOD. The PCON register bits are shown in Register 2-6.
REGISTER 2-6:
PCON - POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0 -- bit 7 U-0 -- R/W-0 R/W-1 U-0 -- U-0 -- R/W-0 POR R/W-x BOD bit 0 ULPWUE SBODEN
bit 7-6 bit 5
Unimplemented: Read as `0' ULPWUE: Ultra Low-Power Wake-up Enable bit 1 = Ultra Low-Power Wake-up enabled 0 = Ultra Low-Power Wake-up disabled SBODEN: Software BOD Enable bit(1) 1 = BOD enabled 0 = BOD disabled Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOD: Brown-out Detect Status bit 1 = No Brown-out Detect occurred 0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs) Note 1: BODEN<1:0> = 01 in the Configuration Word register for this bit to control the BOD. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 4
bit 3-2 bit 1
bit 0
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PIC12F683
2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.
FIGURE 2-3:
PCH 12 PC 5 8 7
LOADING OF PC IN DIFFERENT SITUATIONS
PCL Instruction with 0 PCL as Destination 8 ALU Result
2.4
Indirect Addressing, INDF and FSR Registers
PCLATH<4:0>
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (Status<7>), as shown in Figure 2-4. A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1.
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 OPCODE<10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, "Implementing a Table Read" (DS00556).
EXAMPLE 2-1:
MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
2.3.2
STACK
The PIC12F683 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.
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Preliminary
DS41211B-page 17
PIC12F683
FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F683
Indirect Addressing 0 IRP(1) 7 File Select Register 0 Direct Addressing RP1
(1)
RP0
6
From Opcode
Bank Select
Location Select 00 00h 01 10 11
Bank Select 180h
Location Select
Data Memory
Not Used
7Fh Bank 0 For memory map detail, see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. Bank 1 Bank 2 Bank 3
1FFh
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PIC12F683
3.0
3.1
CLOCK SOURCES
Overview
The PIC12F683 can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. EC - External clock with I/O on GP4. LP - Low gain crystal or Ceramic Resonator Oscillator mode. XT - Medium gain crystal or Ceramic Resonator Oscillator mode. HS - High gain crystal or Ceramic Resonator mode. RC - External Resistor-Capacitor (RC) with FOSC/4 output on GP4 RCIO - External Resistor-Capacitor with I/O on GP4. INTRC - Internal oscillator with FOSC/4 output on GP4 and I/O on GP5. INTRCIO - Internal oscillator with I/O on GP4 and GP5.
The PIC12F683 has a wide variety of clock sources and selection features to allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the PIC12F683 clock sources. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal via software. * Two-Speed Clock Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch to the internal oscillator.
Clock source modes are configured by the FOSC<2:0> bits in the Configuration Word register (see Section 12.0 "Special Features of the CPU"). The internal clock can be generated by two oscillators. The HFINTOSC is a high-frequency calibrated oscillator. The LFINTOSC is a low-frequency uncalibrated oscillator.
FIGURE 3-1:
PIC12F683 CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0> (Configuration Word) SCS (OSCCON<0>)
External Oscillator OSC2 Sleep OSC1 IRCF<2:0> (OSCCON<6:4>) 8 MHz Internal Oscillator 4 MHz 2 MHz Postscaler 101 100 500 kHz 250 kHz 125 kHz LFINTOSC 31 kHz 31 kHz 011 010 001 000 MUX 1 MHz HFINTOSC 8 MHz 111 110
LP, XT, HS, RC, RCIO, EC MUX
System Clock (CPU and Peripherals)
Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
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Preliminary
DS41211B-page 19
PIC12F683
3.2 Clock Source Modes 3.3
3.3.1
External Clock Modes
OSCILLATOR START-UP TIMER (OST)
Clock source modes can be classified as external or internal. * External clock modes rely on external circuitry for the clock source. Examples are oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC mode) circuits. * Internal clock sources are contained internally within the PIC12F683. The PIC12F683 has two internal oscillators: the 8 MHz High-Frequency Internal Oscillator (HFINTOSC) and 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (see Section 3.5 "Clock Switching").
If the PIC12F683 is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from the OSC1 pin, following a Power-on Reset (POR) and the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the PIC12F683. When switching between clock sources a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 3-1. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Startup mode can be selected (see Section 3.6 "Two-Speed Clock Start-up Mode").
TABLE 3-1:
OSCILLATOR DELAY EXAMPLES
Switch To LFINTOSC HFINTOSC EC, RC EC, RC LP, XT, HS HFINTOSC Frequency 31 kHz 125 kHz-8 MHz DC - 20 MHz DC - 20 MHz 31 kHz-20 MHz 125 kHz-8 MHz 1024 Clock Cycles (OST) 1 s (approx.) Oscillator Delay 5 s-10 s (approx.) CPU Start-up(1)
Switch From Sleep/POR Sleep/POR LFINTOSC (31 kHz) Sleep/POR LFINTOSC (31 kHz) Note 1:
The 5 s-10 s start-up delay is based on a 1 MHz system clock.
3.3.2
EC MODE
FIGURE 3-2:
The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 pin and the GP5 pin is available for general purpose I/O. Figure 3-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC12F683 design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC12F683 GP4 I/O (OSC2)
Clock from Ext. System
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2004 Microchip Technology Inc.
PIC12F683
3.3.3 LP, XT, HS MODES FIGURE 3-4:
The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to the OSC1 and OSC2 pins (Figure 3-1). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification, for example, AT-cut quartz crystal resonators. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting, for example, AT-cut quartz crystal resonators or ceramic resonators. Figure 3-3 and Figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively.
C1
CERAMIC RESONATOR OPERATION (XT OR HS MODE)
PIC12F683
OSC1 To Internal Logic RP(3) RF(2) Sleep
C2 Ceramic Resonator
OSC2 RS(1)
Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the oscillator mode selected (typically between 2 M to 10 M). 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation (typical value 1 M).
3.3.4
EXTERNAL RC MODES
FIGURE 3-3:
QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE)
PIC12F683
OSC1
The External Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes, RC and RCIO. In RC mode, the RC circuit connects to the OSC1 pin. The OSC2/CLKOUT pin outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the RC mode connections.
C1
To Internal Logic Quartz Crystal OSC2 RS(1) RF(2) Sleep
FIGURE 3-5:
VDD REXT
RC MODE
C2
OSC1 A series resistor (RS) may be required for quartz crystals with low drive level. The value of RF varies with the oscillator mode selected (typically between 2 M to 10 M). CEXT VSS FOSC/4 Recommended values:
Note 1: 2:
Internal Clock
PIC12F683 OSC2/CLKOUT 3 k REXT 100 k CEXT > 20 pF
Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application.
In RCIO mode, the RC circuit is connected to the OSC1 pin. The OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 4 of GPIO (GP4). Figure 3-6 shows the RCIO mode connections.
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Preliminary
DS41211B-page 21
PIC12F683
FIGURE 3-6:
VDD REXT OSC1 CEXT VSS GP4 Recommended values: I/O (OSC2) 3 k REXT 100 k CEXT > 20 pF PIC12F683 Internal Clock
RCIO MODE
3.4.1
INTRC AND INTRCIO MODES
The INTRC and INTRCIO modes configure the internal oscillators as the system clock source when the device is programmed using the Oscillator Selection (FOSC) bits in the Configuration Word register (Register 12-1). In INTRC mode, the OSC1 pin is available for general purpose I/O. The OSC2/CLKOUT pin outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTRCIO mode, the OSC1 and OSC2 pins are available for general purpose I/O.
The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: * threshold voltage variation * component tolerances * packaging variations in capacitances
3.4.2
HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered approximately 12% via software using the OSCTUNE register (Register 3-1). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). One of seven frequencies can be selected via software using the IRCF bits (see Section 3.4.4 "Frequency Select Bits (IRCF)"). The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz (IRCF 000) as the system clock source (SCS = 1), or when Two-Speed Start-up is enabled (IESO = 1 and IRCF 000). The HF Internal Oscillator (HTS) bit (OSCCON<2>) indicates whether the HFINTOSC is stable or not.
3.4
Internal Clock Modes
The PIC12F683 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted 12% via software using the OSCTUNE register (Register 3-1). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at approximately 31 kHz.
2.
The system clock speed can be selected via software using the Internal Oscillator Frequency Select (IRCF) bits. The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (see Section 3.5 "Clock Switching").
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Preliminary
2004 Microchip Technology Inc.
PIC12F683
3.4.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-1). The OSCTUNE register has a tuning range of 12%. The default value of the OSCTUNE register is `0'. The value is a 5-bit two's complement number. Due to process variation, the monotonicity and frequency step cannot be specified. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. The HFINTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.
REGISTER 3-1:
OSCTUNE - OSCILLATOR TUNING RESISTOR (ADDRESS: 90h)
U-0 -- bit 7 U-0 -- U-0 -- R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
bit 7-5 bit 4-0
Unimplemented: Read as `0' TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = * * * 00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 = * * * 10000 = Minimum frequency Legend: R = Readable bit - n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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Preliminary
DS41211B-page 23
PIC12F683
3.4.3 LFINTOSC 3.4.5
The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 "Frequency Select Bits (IRCF)"). The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF = 000) as the system clock source (SCS = 1), or when any of the following are enabled: * * * * Two-Speed Start-up (IESO = 1 and IRCF = 000) Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
HF AND LF INTOSC CLOCK SWITCH TIMING
When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power. If this is the case, there is a 10 s delay after the IRCF bits are modified before the frequency selection takes place. The LTS/HTS bits will reflect the current active status of the LFINTOSC and the HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. IRCF bits are modified. If the new clock is shut down, a 10 s clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. CLKOUT is held low and the clock switch circuitry waits for a rising edge in the new clock. CLKOUT is now connected with the new clock. HTS/LTS bits are updated as required. Clock switch is complete.
The LF Internal Oscillator (LTS) bit (OSCCON<1>) indicates whether the LFINTOSC is stable or not.
3.4.4
FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency select bits, IRCF<2:0> (OSCCON<6:4>), select the frequency output of the internal oscillators. One of eight frequencies can be selected via software: * * * * * * * * 8 MHz 4 MHz (Default after Reset) 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz Note: Following any Reset, the IRCF bits are set to `110' and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency.
If the internal oscillator speed selected is between 8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and the new frequencies are derived from the HFINTOSC via the postscaler and multiplexer.
3.5
Clock Switching
The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit.
3.5.1
SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit (OSCCON<0>) selects the system clock source that is used for the CPU and peripherals. * When SCS = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in the Configuration Word register (CONFIG). * When SCS = 1, the system clock source is chosen by the internal oscillator frequency selected by the IRCF bits. After a Reset, SCS is always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or FailSafe Clock Monitor, does not update the SCS bit. The user can monitor the OSTS (OSCCON<3>) to determine the current system clock source.
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2004 Microchip Technology Inc.
PIC12F683
3.5.2 OSCILLATOR START-UP TIME-OUT STATUS BIT 3.6.1 TWO-SPEED START-UP MODE CONFIGURATION
The Oscillator Start-up Time-out Status (OSTS) bit (OSCCON<3>) indicates whether the system clock is running from the external clock source, as defined by the FOSC bits, or from internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. Two-Speed Start-up mode is configured by the following settings: * IESO = 1 (CONFIG<10>) Internal/External Switch Over bit. * SCS = 0. * FOSC configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after PWRT has expired, or * Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.
3.6
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit (OSCCON<3>) to remain clear.
3.6.2
1. 2.
TWO-SPEED START-UP SEQUENCE
When the PIC12F683 is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.3.1 "Oscillator Start-up Timer (OST)"). The OST timer will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit (OSCCON<3>) is set, program execution switches to the external oscillator.
3. 4. 5. 6. 7.
Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF bits (OSCCON<6:4>). OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
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Preliminary
DS41211B-page 25
PIC12F683
3.6.3 CHECKING EXTERNAL/INTERNAL CLOCK STATUS
Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC12F683 is running from the external clock source as defined by the FOSC bits in the Configuration Word register (CONFIG) or the internal oscillator.
FIGURE 3-7:
TWO-SPEED START-UP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
INTOSC TOST T OSC1 0 1 1022 1023
OSC2 Program Counter PC PC + 1 PC + 2
System Clock
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PIC12F683
3.7 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired. active and the WDT is cleared. The SCS bit (OSCCON<0>) is not updated. Enabling FSCM does not affect the LTS bit. The FSCM sample clock is generated by dividing the INTRC clock by 64. This will allow enough time between FSCM sample clocks for a system clock edge to occur. Figure 3-8 shows the FSCM block diagram. On the rising edge of the sample clock, the monitoring latch (CM = 0) will be cleared. On a falling edge of the primary system clock, the monitoring latch will be set (CM = 1). In the event that a falling edge of the sample clock occurs and the monitoring latch is not set, a clock failure has been detected. The assigned internal oscillator is enabled when FSCM is enabled, as reflected by the IRCF. Note: Two-Speed Start-up is automatically enabled when the Fail-Safe Clock Monitor mode is enabled. Primary clocks with a frequency ~488 Hz will be considered failed by the FSCM. A slow starting oscillator can cause an FSCM interrupt.
FIGURE 3-8:
FSCM BLOCK DIAGRAM
Primary Clock
Clock Fail Detector / 64
LFINTOSC Oscillator
Clock Failure Detected
The FSCM function is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG). It is applicable to all external clock options (LP, XT, HS, EC, RC or IO modes). In the event of an external clock failure, the FSCM will set the OSFIF bit (PIR1<2>) and generate an oscillator fail interrupt if the OSFIE bit (PIE1<2>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscillator unless the external clock recovers and the Fail-Safe condition is exited. The frequency of the internal oscillator will depend upon the value contained in the IRCF bits (OSCCON<6:4>). Upon entering the Fail-Safe condition, the OSTS bit (OSCCON<3>) is automatically cleared to reflect that the internal oscillator is
Note:
3.7.1
FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction, or a modification of the SCS bit. While in Fail-Safe condition, the PIC12F683 uses the internal oscillator as the system clock source. The IRCF bits (OSCCON<6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.
FIGURE 3-9:
Sample Clock System Clock Output CM Output (Q)
FSCM TIMING DIAGRAM
Oscillator Failure
Failure Detected OSCFIF
CM Test Note:
CM Test
CM Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
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PIC12F683
3.7.2 RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired. If the external clock is EC or RC mode, monitoring will begin immediately following these events. For LP, XT or HS mode the external oscillator may require a start-up time considerably longer than the FSCM sample clock time or a false clock failure may be detected (see Figure 3-9). To prevent this, the internal oscillator is automatically configured as the system clock and functions until the external clock is stable (the OST has timed out). This is identical to Two-Speed Start-up mode. Once the external oscillator is stable, the LFINTOSC returns to its role as the FSCM source.
Note:
Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit (OSCCON<3>) to verify the oscillator start-up and system clock switchover has successfully completed.
REGISTER 3-2:
OSCCON - OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)
U-0 -- bit 7 R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 R-1 OSTS(1) R-0 HTS R-0 LTS R/W-0 SCS bit 0
bit 7 bit 6-4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0' IRCF<2:0>: Internal Oscillator Frequency Select bits 000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz 101 = 2 MHz 110 = 4 MHz 111 = 8 MHz OSTS: Oscillator Start-up Time-out Status bit 1 = Device is running from the external system clock defined by FOSC<2:0> 0 = Device is running from the internal system clock (HFINTOSC or LFINTOSC) HTS: HFINTOSC (High Frequency - 8 MHz to 125 kHz) Status bit 1 = HFINTOSC is stable 0 = HFINTOSC is not stable LTS: LFINTOSC (Low Frequency - 31 kHz) Stable bit 1 = LFINTOSC is stable 0 = LFINTOSC is not stable SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> Note 1: Bit resets to `0' with Two-Speed Start-up and LP, XT or HS selected as the oscillator mode or Fail-Safe mode is enabled.
Legend: R = Readable bit - n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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TABLE 3-2:
Addr
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOD Value on all other Resets
Name
0Ch 8Ch 8Fh 90h
PIR1 PIE1 OSCCON OSCTUNE
EEIF EEIE -- -- CPD
ADIF ADIE IRCF2 -- CP
CCP1IF CCP1IE IRCF1 --
-- -- IRCF0 TUN4
CMIF CMIE OSTS(2) TUN3 WDTE
OSFIF OSFIE HTS TUN2 FOSC2
TMR2IF TMR1IF 000- 0000 0000 0000 TMR2IE TMR1IE 000- 0000 0000 0000 LTS TUN1 FOSC1 SCS TUN0 FOSC0 -110 x000 -110 x000 ---0 0000 ---u uuuu -- --
2007h(1) CONFIG Legend: Note 1: 2:
MCLRE PWRTE
x = unknown, u = unchanged, -- = unimplemented locations read as `0'. Shaded cells are not used by oscillators. See Register 12-1 for operation of all Configuration Word register bits. See Register 3-2 for details.
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PIC12F683
NOTES:
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PIC12F683
4.0 GPIO PORT
Note: There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Note: Additional information on I/O ports may be found in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023). The ANSEL (9Fh) and CMCON0 (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
EXAMPLE 4-1:
BCF CLRF MOVLW MOVWF BSF CLRF MOVLW MOVWF BCF STATUS,RP0 GPIO 07h CMCON0 STATUS,RP0 ANSEL 0Ch TRISIO STATUS,RP0
INITIALIZING GPIO
;Bank 0 ;Init GPIO ;Set GP<2:0> to ;digital I/O ;Bank 1 ;digital I/O ;Set GP<3:2> as inputs ;and set GP<5:4,1:0> ;as outputs ;Bank 0
4.1
GPIO and the TRISIO Registers
GPIO is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISIO. Setting a TRISIO bit (= 1) will make the corresponding GPIO pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISIO bit (= 0) will make the corresponding GPIO pin an output (i.e., put the contents of the output latch on the selected pin). The exception is GP3, which is input only and its TRISIO bit will always read as `1'. Example 4-1 shows how to initialize GPIO. Reading the GPIO register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. GP3 reads `0' when MCLRE = 1. The TRISIO register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISIO register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'.
4.2
Additional Pin Functions
Every GPIO pin on the PIC12F683 has an interrupt-onchange option and a weak pull-up option. GP0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions.
4.2.1
WEAK PULL-UPS
Each of the GPIO pins, except GP3, has an individually configurable weak internal pull-up. Control bits WPUx enable or disable each pull-up. Refer to Register 4-3. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the GPPU bit (OPTION<7>). A weak pull-up is automatically enabled for GP3 when configured as MCLR and disabled when GP3 is an I/O. There is no software control of the MCLR pull-up.
REGISTER 4-1:
GPIO - GENERAL PURPOSE I/O REGISTER (ADDRESS: 05h)
U-0 -- bit 7 U-0 -- R/W-x GP5 R/W-x GP4 R/W-x GP3 R/W-x GP2 R/W-0 GP1 R/W-0 GP0 bit 0
bit 7-6: bit 5-0:
Unimplemented: Read as `0' GPIO<5:0>: GPIO I/O pin 1 = Port pin is > VIH 0 = Port pin is < VIL Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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PIC12F683
REGISTER 4-2: TRISIO - GPIO TRI-STATE REGISTER (ADDRESS: 85h)
U-0 -- bit 7 bit 7-6: bit 5-0: Unimplemented: Read as `0' TRISIO<5:0>: GPIO Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output Note 1: TRISIO<3> always reads `1'. 2: TRISIO<5:4> reads `1' in XT, LP and HS modes. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 TRISIO5 R/W-1 TRISIO4 R-1 TRISIO3 R/W-1 R/W-1 R/W-1 TRISIO0 bit 0 TRISIO2 TRISIO1
REGISTER 4-3:
WPU - WEAK PULL-UP REGISTER (ADDRESS: 95h)
U-0 -- bit 7 U-0 -- R/W-1 WPU5 R/W-1 WPU4 U-0 -- R/W-1 WPU2 R/W-1 WPU1 R/W-1 WPU0 bit 0
bit 7-6 bit 5-4
Unimplemented: Read as `0' WPU<5:4>: Weak Pull-up register bit 1 = Pull-up enabled 0 = Pull-up disabled Unimplemented: Read as `0' WPU<2:0>: Weak Pull-up register bit 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global GPPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in output mode (TRISIO = 0). 3: The GP3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word. 4: WPU<5:4> reads `1' in XT, LP and HS modes. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3 bit 2-0
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PIC12F683
4.2.2 INTERRUPT-ON-CHANGE
Each of the GPIO pins is individually configurable as an interrupt-on-change pin. Control bits IOCx enable or disable the interrupt function for each pin. Refer to Register 4-4. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of GPIO. The `mismatch' outputs of the last read are OR'd together to set the GPIO Change Interrupt Flag bit (GPIF) in the INTCON register. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) b) Any read or write of GPIO. This will end the mismatch condition, then Clear the flag bit GPIF.
A mismatch condition will continue to set flag bit GPIF. Reading GPIO will end the mismatch condition and allow flag bit GPIF to be cleared. The latch holding the last read value is not affected by a MCLR nor BOD Reset. After these resets, the GPIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the GPIF interrupt flag may not get set.
REGISTER 4-4:
IOC - INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
U-0 -- bit 7 U-0 -- R/W-0 IOC5 R/W-0 IOC4 R/W-0 IOC3 R/W-0 IOC2 R/W-0 IOC1 R/W-0 IOC0 bit 0
bit 7-6 bit 5-0
Unimplemented: Read as `0' IOC<5:0>: Interrupt-on-change GPIO Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOC<5:4> reads `1' in XT, LP and HS modes. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
4.2.3
ULTRA LOW-POWER WAKE-UP
The Ultra Low-Power Wake-up (ULPWU) on GP0 allows a slow falling voltage to generate an interrupton-change on GP0 without excess current consumption. The mode is selected by setting the ULPWUE bit (PCON<5>). This enables a small current sink which can be used to discharge a capacitor on GP0. To use this feature, the GP0 pin is configured to output `1' to charge the capacitor, interrupt-on-change for GP0 is enabled and GP0 is configured as an input. The ULPWUE bit is set to begin the discharge and a SLEEP instruction is performed. When the voltage on GP0 drops below VIL, an interrupt will be generated which will cause the device to wake-up. Depending on the state of the GIE bit (INTCON<7>), the device will either jump to the interrupt vector (0004h) or execute the next instruction when the interrupt event occurs. See Section 4.2.2 "Interrupt-on-change" and Section 12.4.3 "GPIO Interrupt" for more information.
This feature provides a low-power technique for periodically waking up the device from Sleep. The time-out is dependent on the discharge time of the RC circuit on GP0. See Example 4-2 for initializing the Ultra Low-Power Wake-up module. The series resistor provides overcurrent protection for the GP0 pin and can allow for software calibration of the timeout (see Figure 4-1). A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired interrupt delay. This technique will compensate for the affects of temperature, voltage and component accuracy. The Ultra Low-Power Wake-up peripheral can also be configured as a simple Programmable Low-Voltage Detect or temperature sensor. Note: For more information, refer to the Application Note AN879, "Using the Microchip Ultra Low-Power Wake-up Module" (DS00879).
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PIC12F683
EXAMPLE 4-2:
BCF BSF MOVLW MOVWF BSF BCF BCF CALL BSF BSF BSF MOVLW MOVWF SLEEP
ULTRA LOW-POWER WAKE-UP INITIALIZATION
;Bank 0 ;Set GP0 data latch ;Turn off ; comparator ;Bank 1 ;GP0 to digital I/O ;Output high to ; charge capacitor ;Enable ULP Wake-up ;Select GP0 IOC ;GP0 to input ;Enable interrupt ; and clear flag ;Wait for IOC
4.2.4
PIN DESCRIPTIONS AND DIAGRAMS
STATUS,RP0 GPIO,0 H'7' CMCON0 STATUS,RP0 ANSEL,0 TRISIO,0 CapDelay PCON,ULPWUE IOC,0 TRISIO,0 B'10001000' INTCON
Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this data sheet.
4.2.4.1
GP0/AN0/CIN+/ICSPDAT/ULPWU
Figure 4-1 shows the diagram for this pin. The GP0 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D an analog input to the comparator an analog input to the Ultra Low-Power Wake-up In-Circuit Serial Programming data
FIGURE 4-1:
BLOCK DIAGRAM OF GP0
Analog Input Mode(1) VDD Data Bus WR WPU RD WPU D Q Weak GPPU
CK Q
VDD
D WR GPIO
Q I/O pin
CK Q
VSS
+ D WR TRISIO RD TRISIO RD GPIO D WR IOC RD IOC Q Q D EN Q D EN RD GPIO To Comparator To A/D Converter Note 1: Comparator mode and ANSEL determines Analog Input mode. Q3 Q IULP 0 Analog Input Mode(1) 1 VSS ULPWUE
VT
CK Q
CK Q
Interrupt-onChange
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PIC12F683
4.2.4.2 GP1/AN1/CIN-/VREF/ICSPCLK 4.2.4.3 GP2/AN2/T0CKI/INT/COUT/CCP1
Figure 4-1 shows the diagram for this pin. The GP1 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D a analog input to the comparator a voltage reference input for the A/D In-Circuit Serial Programming clock Figure 4-3 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: * * * * * * a general purpose I/O an analog input for the A/D the clock input for TMR0 an external edge triggered interrupt a digital output from the comparator a digital input/output for the CCP (refer to Section 11.0 "Capture/Compare/PWM (CCP) Module").
FIGURE 4-2:
Data Bus WR WPU RD WPU
BLOCK DIAGRAM OF GP1
Analog Input Mode(1) VDD Weak GPPU
D
Q
FIGURE 4-3:
Data Bus WR WPU RD WPU
BLOCK DIAGRAM OF GP2
Analog Input Mode VDD Weak GPPU COUT Enable Analog Input Mode VDD
CK Q
D CK
Q Q
D WR GPIO
Q
VDD
CK Q D I/O pin D Q VSS Analog Input Mode(1) WR TRISIO RD TRISIO Q D EN Q3 WR IOC RD IOC RD GPIO To Comparator To A/D Converter Interrupt-onchange RD GPIO D CK Q D CK Q Q WR GPIO CK Q Q
COUT
1 0 I/O pin
WR TRISIO RD TRISIO RD GPIO
CK Q
VSS Analog Input Mode
D WR IOC RD IOC
Q
CK Q
Q
D EN
Q Q
D EN Q3
Interrupt-onchange
Q
D EN
RD GPIO Note 1: Comparator mode and ANSEL determines Analog Input mode.
To TMR0 To INT To A/D Converter Note 1: Comparator mode and ANSEL determines Analog Input mode.
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Preliminary
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PIC12F683
4.2.4.4 GP3/MCLR/VPP 4.2.4.5 GP4/AN3/T1G/OSC2/CLKOUT
Figure 4-4 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: * a general purpose input * as Master Clear Reset with weak pull-up Figure 4-5 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D a TMR1 gate input a crystal/resonator connection a clock output
FIGURE 4-4:
BLOCK DIAGRAM OF GP3
VDD MCLRE Weak
FIGURE 4-5:
Input pin
BLOCK DIAGRAM OF GP4
Analog Input Mode CLK(1) Modes VDD Weak GPPU Oscillator Circuit OSC1 CLKOUT Enable VDD
Data Bus RD TRISIO RD GPIO D WR IOC RD IOC CK Q
Reset VSS
MCLRE
Data Bus WR WPU RD WPU
D CK
Q Q
MCLRE
VSS
Q Q
D EN Q3
Q
D EN WR GPIO D Q Fosc/4 1 0 CLKOUT Enable VSS D WR TRISIO RD TRISIO RD GPIO D WR IOC RD IOC Q Q D EN Q D EN Q3 Q CK Q INTOSC/ RC/EC(2) CLKOUT Enable Analog Input Mode I/O pin
Interrupt-onchange
CK Q
RD GPIO
CK Q
Interrupt-onchange
RD GPIO To T1G To A/D Converter Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. 2: With CLKOUT option.
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PIC12F683
4.2.4.6 GP5/T1CKI/OSC1/CLKIN
Figure 4-6 shows the diagram for this pin. The GP5 pin is configurable to function as one of the following: * * * * a general purpose I/O a TMR1 clock input a crystal/resonator connection a clock input
FIGURE 4-6:
BLOCK DIAGRAM OF GP5
INTOSC Mode
Data Bus WR WPU RD WPU
TMR1LPEN(1) VDD Weak
D CK
Q Q GPPU Oscillator Circuit OSC2
D WR GPIO CK
Q Q
VDD
I/O pin D WR TRISIO RD TRISIO RD GPIO D WR IOC RD IOC Q D EN Interrupt-onchange RD GPIO To TMR1 or CLKGEN CK Q Q Q EN Q3 D CK Q Q INTOSC Mode (1) VSS
Note
1: Timer1 LP oscillator enabled. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed.
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TABLE 4-1:
Addr 05h 19h 81h 85h 95h 96h 9Fh Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
Bit 7 -- GIE -- -- -- -- -- Bit 6 -- PEIE COUT -- -- -- ADCS2 Bit 5 GP5 T0IE -- T0CS WPU5 IOC5 ADCS1 Bit 4 GP4 INTE CINV T0SE WPU4 IOC4 ADCS0 Bit 3 GP3 GPIE CIS PSA -- IOC3 ANS3 Bit 2 GP2 T0IF CM2 PS2 WPU2 IOC2 ANS2 Bit 1 GP1 INTF CM1 PS1 WPU1 IOC1 ANS1 Bit 0 GP0 GPIF CM0 PS0 WPU0 IOC0 ANS0 Value on: POR, BOD Value on all other Resets
Name GPIO CMCON0 OPTION_REG TRISIO WPU IOC ANSEL
--xx xx00 --uu uu00 0000 0000 0000 0000 -0-0 0000 -0-0 0000 1111 1111 1111 1111 --11 -111 --11 -111 --00 0000 --00 0000 -000 1111 -000 1111
0Bh/8Bh INTCON
GPPU INTEDG
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
x = unknown, u = unchanged, -- = unimplemented locations read as `0'. Shaded cells are not used by GPIO.
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PIC12F683
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin GP2/T0CKI. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION_REG<4>). Clearing the T0SE bit selects the rising edge. Note: Counter mode has specific external clock requirements. Additional information on these requirements is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023).
Figure 5-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. Note: Additional information on the Timer0 module is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
5.2
Timer0 Interrupt
5.1
Timer0 Operation
Timer mode is selected by clearing the T0CS bit (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
A Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit (INTCON<2>). The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep.
FIGURE 5-1:
CLKOUT (= FOSC/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 1 1 SYNC 2 Cycles 0 0 8-bit Prescaler 1 8 Set Flag bit T0IF on Overflow PSA TMR0 8
T0CKI pin T0SE T0CS
WDTE SWDTEN
PSA
PS<2:0> 16-bit Prescaler 31 kHz INTRC Watchdog Timer WDTPS<3:0>
1 WDT Time-out
16
0
PSA
Note 1: T0SE, T0CS, PSA and PS<2:0> are bits in the Option register, WDTPS<3:0> are bits in the WDTCON register.
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5.3 Using Timer0 with an External Clock
5.4.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device Reset, the following instruction sequence (Example 5-1 and Example 5-2) must be executed when changing the prescaler assignment from Timer0 to WDT.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. Note: The ANSEL (9Fh) and CMCON0 (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
EXAMPLE 5-1:
BCF STATUS,RP0 CLRWDT CLRF TMR0 BSF STATUS,RP0
CHANGING PRESCALER (TIMER0 WDT)
;Bank 0 ;Clear WDT ;Clear TMR0 and ; prescaler ;Bank 1 ;Required if desired ; PS2:PS0 is ; 000 or 001 ; ;Set postscaler to ; desired WDT rate ;Bank 0
5.4
Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. For simplicity, this counter will be referred to as "prescaler" throughout this data sheet. The prescaler assignment is controlled in software by the control bit PSA (OPTION_REG<3>). Clearing the PSA bit will assign the prescaler to Timer0. Prescale values are selectable via the PS<2:0> bits (OPTION_REG<2:0>). The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1, x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer.
MOVLW b'00101111' MOVWF OPTION_REG CLRWDT MOVLW MOVWF BCF b'00101xxx' OPTION_REG STATUS,RP0
To change prescaler from the WDT to the TMR0 module, use the sequence shown in Example 5-2. This precaution must be taken even if the WDT is disabled.
EXAMPLE 5-2:
CLRWDT BSF MOVLW STATUS,RP0
CHANGING PRESCALER (WDT TIMER0)
;Clear WDT and ; prescaler ;Bank 1 ;Select TMR0, ; prescale, and ; clock source ; ;Bank 0
b'xxxx0xxx'
MOVWF BCF
OPTION_REG STATUS,RP0
TABLE 5-1:
Addr 01h 81h 85h Legend:
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD Value on all other Resets
Name TMR0
Timer0 Module Register GIE -- PEIE INTEDG -- T0IE T0CS INTE T0SE GPIE PSA T0IF PS2 INTF PS1 GPIF PS0
xxxx xxxx uuuu uuuu 0000 0000 0000 0000 1111 1111 1111 1111
0Bh/8Bh INTCON TRISIO
OPTION_REG GPPU
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
-- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
DS41211B-page 40
Preliminary
2004 Microchip Technology Inc.
PIC12F683
6.0 TIMER1 MODULE WITH GATE CONTROL
The Timer1 Control register (T1CON), shown in Register 6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module. Note: Additional information on timer modules is available in the PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023).
The PIC12F683 has a 16-bit timer. Figure 6-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: 16-bit timer/counter (TMR1H:TMR1L) Readable and writable Internal or external clock selection Synchronous or asynchronous operation Interrupt on overflow from FFFFh to 0000h Wake-up upon overflow (Asynchronous mode) Optional external enable input - Selectable gate source: T1G or COUT (T1GSS) - Selectable gate polarity (T1GINV) * Optional LP oscillator * * * * * * *
FIGURE 6-1:
TIMER1 ON THE PIC12F683 BLOCK DIAGRAM
TMR1ON TMR1GE TMR1ON TMR1GE To Comparator Module TMR1 Clock Synchronized 0 Clock Input 1
(2)
T1GINV
Set Flag bit TMR1IF on Overflow
TMR1(1) TMR1H Oscillator TMR1L
OSC1/T1CKI FOSC/4 Internal Clock
T1SYNC 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS<1:0> TMR1CS 1 Sleep Input Synchronize det
OSC2/T1G INTOSC without CLKOUT T1OSCEN
COUT
0 T1GSS
Note 1: 2:
Timer1 increments on the rising edge. ST Buffer is low-power type when using LP oscillator or high-speed type when using T1CKI.
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 41
PIC12F683
6.1 Timer1 Modes of Operation 6.3 Timer1 Prescaler
Timer1 can operate in one of three modes: * 16-bit timer with prescaler * 16-bit synchronous counter * 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. In Counter and Timer modules, the counter/timer clock can be gated by the Timer 1 gate, which can be selected as either the T1G pin or the comparator output. If an external clock oscillator is needed (and the microcontroller is using the INTOSC w/o CLKOUT), Timer1 can use the LP oscillator as a clock source. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge. Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits (T1CON<5:4>) control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
6.4
Timer1 Gate
Timer1 gate source is software configurable to be the T1G pin or the output of the comparator. This allows the device to directly time external events using T1G or analog events using the comparator. See CMCON1 (Register 8-2) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D Converters, see the Microchip web site (www.microchip.com). Note: TMR1GE bit (T1CON<6>) must be set to use either T1G or COUT as the Timer1 gate source. See Register 8-2 for more information on selecting the Timer1 gate source.
6.2
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1<0>) is set. To enable the interrupt on rollover, you must set these bits: * Timer1 interrupt enable bit (PIE1<0>) * PEIE bit (INTCON<6>) * GIE bit (INTCON<7>). The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts.
Timer1 gate can be inverted by using the T1GINV bit (T1CON<7>), whether it originates from the T1G pin or the comparator output. This configures Timer1 to measure either the active-high or active-low time between events.
FIGURE 6-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
DS41211B-page 42
Preliminary
2004 Microchip Technology Inc.
PIC12F683
REGISTER 6-1: T1CON - TIMER1 CONTROL REGISTER (ADDRESS: 10h)
R/W-0 T1GINV bit 7 bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is inverted 0 = Timer1 gate is not inverted TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored. If TMR1ON = 1: 1 = Timer1 is on if Timer1 gate is not active 0 = Timer1 is on T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored. T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit (CMCON1<1>), as a Timer1 gate source. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0 TMR1GE T1CKPS1 T1CKPS0 T1OSCEN
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 43
PIC12F683
6.5 Timer1 Operation in Asynchronous Counter Mode 6.6 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated up to 32 kHz. It will continue to run during Sleep. It is primarily intended for a 32 kHz crystal. Table 3-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator. As with the system LP oscillator, the user must provide a software time delay to ensure proper oscillator start-up. TRISIO5 and TRISIO4 bits are set when the Timer1 oscillator is enabled. GP5 and GP4 read as `0' and TRISIO5 and TRISIO4 bits read as `1'. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 6.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: The ANSEL (9Fh) and CMCON0 (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
6.5.1
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Examples in the "PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode.
6.7
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * Timer1 must be on (T1CON<0>) * TMR1IE bit (PIE1<0>) must be set * PEIE bit (INTCON<6>) must be set The device will wake-up on an overflow. If the GIE bit (INTCON<7>) is set, the device will wake-up and jump to the Interrupt Service Routine (0004h) on an overflow. If the GIE bit is clear, execution will continue with the next instruction.
TABLE 6-1:
Addr 0Bh/ 8Bh 0Ch 0Eh 0Fh 10h 1Ah 8Ch Name INTCON PIR1 TMR1L TMR1H T1CON CMCON1 PIE1
REGISTERS ASSOCIATED WITH TIMER1
Bit 7 GIE EEIF Bit 6 PEIE ADIF Bit 5 T0IE CCP1IF Bit 4 INTE -- Bit 3 GPIE CMIF Bit 2 T0IF OSFIF Bit 1 INTF TMR2IF Bit 0 GPIF Value on POR, BOD Value on all other Resets
0000 0000 0000 0000
TMR1IF 000- 0000 000- 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- EEIE -- ADIE -- CCP1IE -- -- -- CMIE -- OSFIE T1GSS TMR2IE
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu CMSYNC ---- --10 ---- --10 TMR1IE 000- 0000 000- 0000
Legend:
x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
DS41211B-page 44
Preliminary
2004 Microchip Technology Inc.
PIC12F683
7.0
* * * * * *
TIMER2 MODULE
7.1
Timer2 Operation
The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match with PR2
Timer2 has a control register shown in Register 7-1. TMR2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. Figure 7-1 is a simplified block diagram of the Timer2 module. The prescaler and postscaler selection of Timer2 are controlled by this register.
Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, T2CKPS<1:0> (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written.
REGISTER 7-1:
T2CON - TIMER2 CONTROL REGISTER (ADDRESS: 12h)
U-0 -- bit 7 R/W-0 TOUTPS3 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 R/W-0 R/W-0 T2CKPS0 bit 0 TMR2ON T2CKPS1
bit 7 bit 6-3
Unimplemented: Read as `0' TOUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 postscale 0001 = 1:2 postscale * * * 1111 = 1:16 postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 2
bit 1-0
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 45
PIC12F683
7.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
TMR2 Output Sets Flag bit TMR2IF
FOSC/4
Prescaler 1:1, 1:4, 1:16 2 T2CKPS<1:0>
TMR2
Reset
Comparator EQ PR2
Postscaler 1:1 to 1:16 4 TOUTPS<3:0>
TABLE 7-1:
Addr 0Bh/ 8Bh 0Ch 11h 12h 8Ch 92h Name INTCON PIR1 TMR2 T2CON PIE1 PR2
REGISTERS ASSOCIATED WITH TIMER2
Bit 7 GIE EEIF -- EEIE Bit 6 PEIE ADIF Bit 5 T0IE CCP1IF Bit 4 INTE -- Bit 3 GPIE CMIF Bit 2 T0IF OSFIF Bit 1 INTF TMR2IF Bit 0 GPIF Value on POR, BOD Value on all other Resets
0000 0000 0000 0000
TMR1IF 000- 0000 000- 0000 0000 0000 0000 0000
Holding Register for the 8-bit TMR2 Register ADIE CCP1IE -- CMIE OSFIE TMR2IE
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 TMR1IE 000- 0000 000- 0000 1111 1111 1111 1111
Timer2 Module Period Register
Legend:
x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module.
DS41211B-page 46
Preliminary
2004 Microchip Technology Inc.
PIC12F683
8.0 COMPARATOR MODULE
The comparator module contains one analog comparator. The inputs to the comparator are multiplexed with I/O port pins, GP0 and GP1, while the outputs are multiplexed to GP2. An on-chip Comparator Voltage Reference (CVREF) can also be applied to the inputs of the comparator. The CMCON0 register (Register 8-1) controls the comparator input and output multiplexers. A block diagram of the various comparator configurations is shown in Figure 8-3.
REGISTER 8-1:
CMCON0 - COMPARATOR CONTROL REGISTER 0 (ADDRESS: 19h)
U-0 -- bit 7 R-0 COUT U-0 -- R/W-0 CINV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0
bit 7 bit 6
Unimplemented: Read as `0' COUT: Comparator Output bit When CINV = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CINV = 1: 1 = VIN+ < VIN0 = VIN+ > VINUnimplemented: Read as `0' CINV: Comparator Output Inversion bit 1 = Output inverted 0 = Output not inverted CIS: Comparator Input Switch bit When CM<2:0> = 110 or 101: 1 = VIN- connects to CIN+ 0 = VIN- connects to CINCM<2:0>: Comparator Mode bits Figure 8-3 shows the Comparator modes and CM<2:0> bit settings. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 5 bit 4
bit 3
bit 2
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 47
PIC12F683
8.1 Comparator Operation
FIGURE 8-1:
VIN+ VIN-
SINGLE COMPARATOR
+ -
A single comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 8-1 represent the uncertainty due to input offsets and response time. Note: To use CIN+ and CIN- pins as analog inputs, the appropriate bits must be programmed in the CMCON0 (19h) register.
Output
VINVIN- VIN+ VIN+
Output Output
The polarity of the comparator output can be inverted by setting the CINV bit (CMCON0<4>). Clearing CINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 8-1.
8.2
Analog Input Connection Considerations
TABLE 8-1:
OUTPUT STATE VS. INPUT CONDITIONS
CINV 0 0 1 1 COUT 0 1 1 0
Input Conditions VIN- > VIN+ VIN- < VIN+ VIN- > VIN+ VIN- < VIN+
A simplified circuit for an analog input is shown in Figure 8-2. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. Note 1: When reading the GPIO register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as analog inputs according to the input specification. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified.
FIGURE 8-2:
ANALOG INPUT MODEL
VDD Rs < 10K AIN VT = 0.6V RIC
VA
CPIN 5 pF
VT = 0.6V
ILEAKAGE 500 nA
Legend:
CPIN VT ILEAKAGE RIC RS VA
Vss = Input Capacitance = Threshold Voltage = Leakage Current at the pin due to various junctions = Interconnect Resistance = Source Impedance = Analog Voltage
DS41211B-page 48
Preliminary
2004 Microchip Technology Inc.
PIC12F683
8.3 Comparator Configuration
Note: There are eight modes of operation for the comparator. The CMCON0 register is used to select these modes. Figure 8-3 shows the eight possible modes. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 15.0 "Electrical Specifications". Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur.
FIGURE 8-3:
CM<2:0> = 000
COMPARATOR I/O OPERATING MODES
Comparator Off (Lowest Power) CM<2:0> = 111
Comparator Reset (POR Default Value - Low Power)
GP1/CINGP0/CIN+ GP2/COUT
A A D Off (Read as `0')
GP1/CINGP0/CIN+ GP2/COUT
D D D Off (Read as `0')
Comparator without Output CM<2:0> = 010
Comparator w/o Output and with Internal Reference CM<2:0> = 100
GP1/CINGP0/CIN+ GP2/COUT
A A D COUT
GP1/CINGP0/CIN+ GP2/COUT
A D D From CVREF Module COUT
Comparator with Output and Internal Reference CM<2:0> = 011
Multiplexed Input with Internal Reference and Output CM<2:0> = 101
GP1/CINGP0/CIN+ GP2/COUT
A D D From CVREF Module COUT
GP1/CINGP0/CIN+ GP2/COUT
A A D From CVREF Module CIS = 0 CIS = 1 COUT
Comparator with Output CM<2:0> = 001
Multiplexed Input with Internal Reference CM<2:0> = 110
GP1/CINGP0/CIN+ GP2/COUT
A A D COUT
GP1/CINGP0/CIN+ GP2/COUT
A A D From CVREF Module CIS = 0 CIS = 1 COUT
Legend: A = Analog Input, ports always read `0' D = Digital Input
CIS = Comparator Input Switch (CMCON0<3>)
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 49
PIC12F683
FIGURE 8-4: COMPARATOR OUTPUT BLOCK DIAGRAM
MULTIPLEX Port Pins CMSYNC To TMR1 0 To COUT pin 1 Q EN D TMR1 Clock Source(1)
CINV
To Data Bus
Q EN RD CMCON
D Q3
Set CMIF bit
Q
D EN
CL
RD CMCON
Reset Note 1: Comparator output is latched on falling edge of T1 clock source.
REGISTER 8-2:
CMCON1 - COMPARATOR CONTROL REGISTER 1 (ADDRESS: 1Ah)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 T1GSS R/W-0 CMSYNC bit 0
bit 7-2: bit 1
Unimplemented: Read as `0' T1GSS: Timer1 Gate Source Select bit 1 = Timer1 gate source is T1G pin (GP4 must be configured as digital input) 0 = Timer1 gate source is comparator output CMSYNC: Comparator Synchronize bit 1 = COUT output synchronized with falling edge of Timer1 clock 0 = COUT output not synchronized with Timer1 clock Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
DS41211B-page 50
Preliminary
2004 Microchip Technology Inc.
PIC12F683
8.4 Comparator Output 8.5 Comparator Interrupt
The comparator output is read through the CMCON0 register. This bit is read-only. The comparator output may also be directly output to the GP2 pin. When enabled, multiplexors in the output path of the GP2 pin will switch and the output will be the unsynchronized output of the comparator. The uncertainty of the comparator is related to the input offset voltage and the response time given in the specifications. Figure 8-4 shows the output block diagram for the comparator. The TRISIO bit will still function as an output enable/ disable for the GP2 pin while in this mode. The polarity of the comparator outputs can be changed using the CINV bit (CMCON0<4>). Timer1 gate source can be configured to use the T1G pin or the comparator output as selected by the T1GSS bit (CMCON1<1>). This feature can be used to time the duration or interval of analog events. The output of the comparator can also be synchronized with Timer1 by setting the CMSYNC bit (CMCON1<0>). When enabled, the output of the comparator is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator is latched after the prescaler. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See Figure 8-4, Comparator Output Block Diagram and Figure 6-1, Timer1 on the PIC12F683 Block Diagram for more information. It is recommended to synchronize the comparator with Timer1 by setting the CMSYNC bit when the comparator is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment. The comparator interrupt flag is set whenever there is a change in the output value of the comparator. Software will need to maintain information about the status of the output bit, as read from CMCON0<6>, to determine the actual change that has occurred. The CMIF bit (PIR1<3>) is the Comparator Interrupt Flag. This bit must be reset in software by clearing it to `0'. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE1<3>) and the PEIE bit (INTCON<6>) must be set to enable the interrupts. In addition, the GIE bit must also be set. If any of these bits are cleared, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON0. This will end the mismatch condition. Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF. Reading CMCON0 will end the mismatch condition and allow flag bit CMIF to be cleared. Note: If a change in the CMCON0 register (COUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR1<3>) interrupt flag may not get set.
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 51
PIC12F683
8.6 Comparator Reference
8.6.2
The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The VRCON register, Register 8-3, controls the voltage reference module shown in Figure 8-5.
VOLTAGE REFERENCE ACCURACY/ERROR
8.6.1
CONFIGURING THE VOLTAGE REFERENCE
The voltage reference can output 32 distinct voltage levels, 16 in a high range and 16 in a low range. The following equation determines the output voltages:
The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 8-5) keep CVREF from approaching VSS or VDD. The exception is when the module is disabled by clearing the VREN bit (VRCON<7>). When disabled, the reference voltage is VSS when VR<3:0> is `0000' and the VRR (VRCON<5>) bit is set. This allows the comparator to detect a zero-crossing and not consume CVREF module current. The voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the comparator voltage reference can be found in Section 15.0 "Electrical Specifications".
EQUATION 8-1:
VRR = 1 (Low Range): CVREF = (VR3:VR0/24) x VDD VRR = 0 (High Range): CVREF = (VDD/4) + (VR3:VR0 X VDD/32)
FIGURE 8-5:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages 8R R R R R
VDD 8R 16-1 Analog MUX VREN CVREF to Comparator Input VRR
VR<3:0>
VREN VR<3:0> = 0000 VRR
DS41211B-page 52
Preliminary
2004 Microchip Technology Inc.
PIC12F683
8.7 Comparator Response Time
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is ensured to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator output. Otherwise, the maximum delay of the comparator should be used (Table 15-8). While the comparator is enabled during Sleep, an interrupt will wake-up the device. If the GIE bit (INTCON<7>) is set, the device will jump to the interrupt vector (0004h) and if clear, continues execution with the next instruction. If the device wakes up from Sleep, the contents of the CMCON0, CMCON1 and VRCON registers are not affected.
8.9
Effects of a Reset
8.8
Operation During Sleep
The comparator and voltage reference, if enabled before entering Sleep mode, remain active during Sleep. This results in higher Sleep currents than shown in the power-down specifications. The additional current consumed by the comparator and the voltage reference is shown separately in the specifications. To minimize power consumption while in Sleep mode, turn off the comparator, CM<2:0> = 111 and voltage reference, VRCON<7> = 0.
A device Reset forces the CMCON0, CMCON1 and VRCON registers to their Reset states. This forces the comparator module to be in the Comparator Reset mode, CM<2:0> = 000 and the voltage reference to its off state. Thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible.
REGISTER 8-3:
VRCON - VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
R/W-0 VREN bit 7 U-0 -- R/W-0 VRR R/W-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0
bit 7
VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS Unimplemented: Read as `0' VRR: CVREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as `0' VR<3:0>: CVREF Value Selection 0 VR <3:0> 15 When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6 bit 5
bit 4 bit 3-0
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TABLE 8-2:
Address Name
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7 GIE EEIF -- -- -- EEIE VREN Bit 6 PEIE ADIF COUT -- -- ADIE -- Bit 5 T0IE CCP1IF -- -- CCPIE VRR Bit 4 INTE -- CINV -- -- -- Bit 3 GPIE CMIF CIS -- CMIE VR3 Bit 2 T0IF OSFIF CM2 -- OSFIE VR2 Bit 1 INTF TMR2IF CM1 T1GSS TMR2IE VR1 Bit 0 GPIF TMR1IF CM0 TRISIO0 TMR1IE VR0 Value on POR, BOD Value on all other Resets
0Bh/8Bh INTCON 0Ch 19h 1Ah 85h 8Ch 99h Legend: PIR1 CMCON0 CMCON1 TRISIO PIE1 VRCON
0000 0000 0000 0000 000- 0000 000- 0000 -0-0 0000 -0-0 0000
CMSYNC ---- --10 ---- --10 --11 1111 --11 1111 000- 0000 000- 0000 0-0- 0000 0-0- 0000
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1
x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the comparator or comparator voltage reference module.
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9.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either VDD or a voltage applied by the VREF pin. Figure 9-1 shows the block diagram of the A/D on the PIC12F683.
The Analog-to-Digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representation of that signal. The PIC12F683 has four analog inputs, multiplexed into one sample and hold
FIGURE 9-1:
A/D BLOCK DIAGRAM
VDD
VCFG = 0
VREF
VCFG = 1
GP0/AN0 GP1/AN1/VREF GP2/AN2 GP4/AN3 GO/DONE ADFM CHS<1:0> ADON ADRESH VSS 10 ADRESL A/D 10
9.1
A/D Configuration and Operation
9.1.3
VOLTAGE REFERENCE
There are two registers available to control the functionality of the A/D module: 1. 2. ADCON0 (Register 9-1) ANSEL (Register 9-2)
9.1.1
ANALOG PORT PINS
There are two options for the voltage reference to the A/D converter: either VDD is used, or an analog voltage applied to VREF is used. The VCFG bit (ADCON0<6>) controls the voltage reference selection. If VCFG is set, then the voltage on the VREF pin is the reference; otherwise, VDD is the reference.
The ANS<3:0> bits (ANSEL<3:0>) and the TRISIO bits control the operation of the A/D port pins. Set the corresponding TRISIO bits to set the pin output driver to its high-impedance state. Likewise, set the corresponding ANSEL bit to disable the digital input buffer. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
9.1.4
CONVERSION CLOCK
The A/D conversion cycle requires 11 TAD. The source of the conversion clock is software selectable via the ADCS bits (ANSEL<6:4>). There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator)
9.1.2
CHANNEL SELECTION
There are four analog channels on the PIC12F683, AN0 through AN3. The CHS bits (ADCON0<3:2>) control which channel is connected to the sample and hold circuit.
For correct conversion, the A/D conversion clock (1/TAD) must be selected to ensure a minimum TAD of 1.6 s. Table 9-1 shows a few TAD calculations for selected frequencies.
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TABLE 9-1:
Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC A/D RC Legend: Note 1: 2: 3: 4:
TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency 20 MHz 100 ns 200 ns
(2) (2)
A/D Clock Source (TAD) ADCS<2:0> 000 100 001 101 010 110 x11
5 MHz 400 ns 800 ns
(2) (2)
4 MHz 500 ns 1.0 s
(2) (2)
1.25 MHz 1.6 s 3.2 s 6.4 s 12.8 s(3) 25.6 s(3) 51.2 s(3) 2-6 s(1,4)
400 ns(2) 800 ns(2) 1.6 s 3.2 s 2-6 s
(1,4)
1.6 s 3.2 s 6.4 s 12.8 s(3) 2-6 s
(1,4)
2.0 s 4.0 s 8.0 s(3) 16.0 s(3) 2-6 s
(1,4)
Shaded cells are outside of recommended range. The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be performed during Sleep.
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9.1.5 STARTING A CONVERSION
The A/D conversion is initiated by setting the GO/DONE bit (ADCON0<1>). When the conversion is complete, the A/D module: * Clears the GO/DONE bit * Sets the ADIF flag (PIR1<6>) * Generates an interrupt (if enabled) If the conversion must be aborted, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete A/D conversion sample. Instead, the ADRESH:ADRESL registers will retain the value of the previous conversion. After an aborted conversion, a 2 TAD delay is required before another acquisition can be initiated. Following the delay, an input acquisition is automatically started on the selected channel. Note: The GO/DONE bit should not be set in the same instruction that turns on the A/D.
FIGURE 9-2:
A/D CONVERSION TAD CYCLES
TAD2 b9 Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) TAD3 b8 TAD4 b7 TAD5 b6 TAD6 b5 TAD7 b4 TAD8 b3 TAD9 TAD10 TAD11 b2 b1 b0
TCY to TAD TAD1
Set GO bit
ADRESH and ADRESL registers are Loaded, GO bit is Cleared, ADIF bit is Set, Holding Capacitor is Connected to Analog Input
9.1.6
CONVERSION OUTPUT
The A/D conversion can be supplied in two formats: left or right shifted. The ADFM bit (ADCON0<7>) controls the output format. Figure 9-3 shows the output formats.
FIGURE 9-3:
10-BIT A/D RESULT FORMAT
ADRESH ADRESL LSB bit 0 bit 7 bit 0
(ADFM = 0)
MSB bit 7
10-bit A/D Result (ADFM = 1) bit 7 MSB bit 0 bit 7
Unimplemented: Read as `0' LSB bit 0
Unimplemented: Read as `0'
10-bit A/D Result
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REGISTER 9-1: ADCON0 - A/D CONTROL REGISTER (ADDRESS: 1Fh)
R/W-0 ADFM bit 7 bit 7 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD Unimplemented: Read as `0' CHS<1:0>: Analog Channel Select bits 00 = Channel 00 (AN0) 01 = Channel 01 (AN1) 10 = Channel 02 (AN2) 11 = Channel 03 (AN3) GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress ADON: A/D Conversion Status bit 1 = A/D converter module is operating 0 = A/D converter is shut off and consumes no operating current Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 VCFG U-0 -- R/W-0 -- R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
bit 6
bit 5-4 bit 3-2
bit 1
bit 0
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REGISTER 9-2: ANSEL - ANALOG SELECT REGISTER (ADDRESS: 9Fh)
U-0 -- bit 7 bit 7 bit 6-4 Unimplemented: Read as `0' ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 ANS<3:0>: Analog Select bits Analog select between analog or digital function on pins ANS<3:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change if available. The corresponding TRISIO bit must be set to input mode in order to allow external control of the voltage on the pin. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0
bit 3-0
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9.1.7 CONFIGURING THE A/D EXAMPLE 9-1: A/D CONVERSION
After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRISIO bits selected as inputs. To determine sample time, see Section 15.0 "Electrical Specifications". After this sample time has elapsed, the A/D conversion can be started. These steps should be followed for an A/D conversion: 1. Configure the A/D module: * Configure analog/digital I/O (ANSEL) * Configure voltage reference (ADCON0) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ANSEL) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit (PIR1<6>) * Set ADIE bit (PIE1<6>) * Set PEIE and GIE bits (INTCON<7:6>) Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0<1>) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared (with interrupts disabled); OR * Waiting for the A/D interrupt Read A/D Result register pair (ADRESH:ADRESL), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.
;This code block configures the A/D ;for polling, Vdd reference, R/C clock ;and GP0 input. ; ;Conversion start & wait for complete ;polling code included. ; BSF STATUS,RP0 ;Bank 1 MOVLW B'01110001' ;A/D RC clock MOVWF ANSEL ;Set GP0 to analog BSF TRISIO,0 ;Set GP0 to input BCF STATUS,RP0 ;Bank 0 MOVLW B'10000001' ;Right, Vdd Vref, AN0 MOVWF ADCON0 CALL SampleTime ;Wait min sample time BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI BSF STATUS,RP0 ;Bank 1 MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO
2.
3. 4. 5.
6. 7.
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9.2 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 9-4. The maximum recommended impedance for analog sources is 10 k. As the impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 91 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. To calculate the minimum acquisition time, TACQ, see the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
EQUATION 9-1:
ACQUISITION TIME
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC = TCOFF = 2 s + TC + [(Temperature - 25C)(0.05 s/C)] TC = CHOLD (RIC + RSS + RS) In(1/2047) = -120 pF (1 k + 7 k +10 k) In(0.0004885) = 16.47 s TACQ = 2 s + 16.47 s + [(50C - 25C)(0.05 s/C)] = 19.72 s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
FIGURE 9-4:
ANALOG INPUT MODEL
VDD RS VA ANx CPIN 5 pF VT = 0.6V RIC 1k ILEAKAGE 500 nA Sampling Switch SS RSS CHOLD = DAC capacitance = 120 pF VSS
VT = 0.6V
Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC)
6V 5V VDD 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (k)
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9.3 A/D Operation During Sleep
The A/D converter module can operate during Sleep. This requires the A/D clock source to be set to the internal oscillator. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion. When the conversion is complete, the GO/DONE bit is cleared and the result is loaded into the ADRESH:ADRESL registers. If the A/D interrupt is enabled, the device awakens from Sleep. If the GIE bit (INTCON<7>) is set, the program counter is set to the interrupt vector (0004h); if GIE is clear, the next instruction is executed. If the A/D interrupt is not enabled, the A/D module is turned off, although the ADON bit remains set. When the A/D clock source is something other than RC, a SLEEP instruction causes the present conversion to be aborted and the A/D module is turned off. The ADON bit remains set.
FIGURE 9-5:
PIC12F683 A/D TRANSFER FUNCTION
Full-Scale Range
3FFh 3FEh 3FDh A/D Output Code 3FCh 3FBh Full-Scale Transition 1 LSB ideal
004h 003h 002h 001h 000h 1 LSB ideal 0V Zero-Scale Transition VREF
Analog Input Voltage
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9.4 Effects of Reset
A device Reset forces all registers to their Reset state. Thus, the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL registers are unchanged.
TABLE 9-2:
Addr 05h 0Bh/ 8Bh 0Ch 1Eh 1Fh 85h 8Ch 9Eh 9Fh Name GPIO INTCON PIR1 ADCON0 TRISIO PIE1 ANSEL
SUMMARY OF A/D REGISTERS
Bit 7 -- GIE EEIF ADFM -- EEIE -- Bit 6 -- PEIE ADIF VCFG -- ADIE ADCS2 Bit 5 GP5 T0IE CCP1IF -- CCPIE ADCS1 Bit 4 GP4 INTE -- -- -- ADCS0 Bit 3 GP3 GPIE CMIF CHS1 CMIE ANS3 Bit 2 GP2 T0IF OSFIF CHS0 OSFIE ANS2 Bit 1 GP1 INTF TMR2IF GO/DONE TRISIO1 TMR2IE ANS1 Bit 0 GP0 GPIF Value on: POR, BOD Value on all other Resets
--xx xxxx --uu uuuu 0000 0000 0000 0000
TMR1IF 000- 0000 000- 0000 xxxx xxxx uuuu uuuu 00-- 0000 00-- 0000 ADON
ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of the right shifted result TRISIO5 TRISIO4 TRISIO3 TRISIO2
TRISIO0 --11 1111 --11 1111 TMR1IE 000- 0000 000- 0000 xxxx xxxx uuuu uuuu -000 1111 -000 1111 ANS0
ADRESL Least Significant 2 bits of the left shifted A/D result or 8 bits of the right shifted result
Legend:
x = unknown, u = unchanged, -- = unimplemented read as `0'. Shaded cells are not used for A/D module.
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NOTES:
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10.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory: * * * * EECON1 EECON2 (not a physically implemented register) EEDAT EEADR The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as from chip-to-chip. Please refer to AC Specifications in Section 15.0 "Electrical Specifications" for exact limits. When the data memory is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access the data EEPROM data and will read zeroes. Additional information on the data EEPROM is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
EEDAT holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. PIC12F683 has 256 bytes of data EEPROM with an address range from 0h to FFh.
REGISTER 10-1:
EEDAT - EEPROM DATA REGISTER (ADDRESS: 9Ah)
R/W-0 EEDAT7 bit 7 R/W-0 EEDAT6 R/W-0 EEDAT5 R/W-0 EEDAT4 R/W-0 EEDAT3 R/W-0 R/W-0 R/W-0 EEDAT0 bit 0 EEDAT2 EEDAT1
bit 7-0
EEDATn: Byte Value to Write to or Read From Data EEPROM bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 10-2:
EEADR - EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
R/W-0 EEADR7 bit 7 R/W-0 EEADR6 R/W-0 EEADR5 R/W-0 EEADR4 R/W-0 EEADR3 R/W-0 R/W-0 R/W-0 bit 0 EEADR2 EEADR1 EEADR0
bit 7-0
EEADR: Specifies One of 256 Locations for EEPROM Read/Write Operation bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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10.1 EECON1 and EECON2 Registers
EECON1 is the control register with four low-order bits physically implemented. The upper four bits are nonimplemented and read as `0'. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit, clear it and rewrite the location. The data and address will be cleared. Therefore, the EEDAT and EEADR registers will need to be re-initialized. Interrupt flag, EEIF bit (PIR1<7>), is set when write is complete. This bit must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the data EEPROM write sequence. Note: The EECON1, EEDAT and EEADR registers should not be modified during a data EEPROM write (WR bit = 1).
REGISTER 10-3:
EECON1 - EEPROM CONTROL REGISTER (ADDRESS: 9Ch)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 7-4 bit 3
Unimplemented: Read as `0' WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOD detect) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set, not cleared, in software.) 0 = Does not initiate an EEPROM read Legend: S = Bit can only be set R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 2
bit 1
bit 0
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10.2 Reading the EEPROM Data Memory
After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. The EEIF bit (PIR1<7>) must be cleared by software.
To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>), as shown in Example 10-1. The data is available, in the very next cycle, in the EEDAT register. Therefore, it can be read in the next instruction. EEDAT holds this value until another read, or until it is written to by the user (during a write operation).
10.4
Write Verify
EXAMPLE 10-1:
BSF MOVLW MOVWF BSF MOVF
DATA EEPROM READ
;Bank 1 ; ;Address to read ;EE Read ;Move data to W
STATUS,RP0 CONFIG_ADDR EEADR EECON1,RD EEDAT,W
Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 10-3) to the desired value to be written.
EXAMPLE 10-3:
BSF MOVF BSF XORWF BTFSS GOTO :
WRITE VERIFY
;Bank 1 ;EEDAT not changed ;from previous write ;YES, Read the ;value written ;Is data the same ;No, handle error ;Yes, continue
STATUS,RP0 EEDAT,W EECON1,RD EEDAT,W STATUS,Z WRITE_ERR
10.3
Writing to the EEPROM Data Memory
To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDAT register. Then the user must follow a specific sequence to initiate the write for each byte, as shown in Example 10-2.
10.4.1
USING THE DATA EEPROM
EXAMPLE 10-2:
BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF
DATA EEPROM WRITE
;Bank 1 ;Enable write ;Disable INTs ;Unlock write ; ; ; ;Start the write ;Enable INTS
STATUS,RP0 EECON1,WREN INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE
Required Sequence
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information. The maximum endurance for any EEPROM cell is specified as Dxxx. D120 or D120A specify a maximum number of writes to any EEPROM location before a refresh is required of infrequently changing memory locations.
10.4.1.1
EEPROM Endurance
The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. A cycle count is executed during the required sequence. Any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the EEPROM. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.
A hypothetical data EEPROM is 64 bytes long and has an endurance of 1M writes. It also has a refresh parameter of 10M writes. If every memory location in the cell were written the maximum number of times, the data EEPROM would fail after 64M write cycles. If every memory location, save one, were written the maximum number of times, the data EEPROM would fail after 63M write cycles but the one remaining location could fail after 10M cycles. If proper refreshes occurred, then the lone memory location would have to be refreshed six times for the data to remain correct.
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10.5 Protection Against Spurious Write 10.6
There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: * brown-out * power glitch * software malfunction
Data EEPROM Operation During Code-Protect
Data memory can be code-protected by programming the CPD bit in the Configuration Word (Register 12-1) to `0'. When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations in program memory to `0' will also help prevent data memory code protection from becoming breached.
TABLE 10-1:
Address 0Bh/8Bh 0Ch 8Ch 9Ah 9Bh 9Ch 9Dh Legend: Note 1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Bit 7 GIE EEIF EEIE Bit 6 PEIE ADIF ADIE Bit 5 T0IE CCP1IF CCP1IE Bit 4 INTE -- -- Bit 3 GPIE CMIF CMIE Bit 2 T0IF OSFIF OSFIE Bit 1 INTF Bit 0 GPIF Value on POR, BOD Value on all other Resets
Name INTCON PIR1 PIE1 EEDAT EEADR EECON1 EECON2
(1)
0000 0000 0000 0000
TMR2IF TMR1IF 000- 0000 000- 0000 TMR2IE TMR1IE 000- 0000 000- 0000
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 -- -- -- -- WRERR WREN WR RD ---- x000 ---- q000 ---- ---- ---- ---EEPROM Control Register 2
x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by data EEPROM module. EECON2 is not a physical register.
DS41211B-page 68
Preliminary
2004 Microchip Technology Inc.
PIC12F683
11.0 CAPTURE/COMPARE/PWM (CCP) MODULE
TABLE 11-1: CCP MODE - TIMER RESOURCES REQUIRED
Timer Resource Timer1 Timer1 Timer2 CCP Mode Capture Compare PWM
The Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: * 16-bit Capture register * 16-bit Compare register * PWM Master/Slave Duty Cycle register Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP. The special event trigger is generated by a compare match and will clear both TMR1H and TMR1L registers.
REGISTER 11-1:
CCP1CON - CCP CONTROL REGISTER 1 (ADDRESS: 15h)
U-0 -- bit 7 U-0 -- R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 R/W-0 R/W-0 CCP1M0 bit 0 CCP1M2 CCP1M1
bit 7-6 bit 5-4
Unimplemented: Read as `0' DC1B<1:0>: PWM Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. CCP1M<3:0>: CCP1 Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected); CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3-0
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 69
PIC12F683
11.1 Capture Mode
11.1.2 TIMER1 MODE SELECTION
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin GP2/AN2/T0CKI/INT/COUT/CCP1. An event is defined as one of the following and is configured by CCP1CON<3:0>: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.
11.1.3
SOFTWARE INTERRUPT
When a capture is made, the interrupt request flag bit, CCP1IF (PIR1<5>), is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value.
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<5>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode.
11.1.4
CCP PRESCALER
11.1.1
CCP1 PIN CONFIGURATION
In Capture mode, the GP2/AN2/T0CKI/INT/COUT/ CCP1 pin should be configured as an input by setting the TRISIO<2> bit. Note: If the GP2/AN2/T0CKI/INT/COUT/CCP1 pin is configured as an output, a write to the port can cause a capture condition.
There are four prescaler settings specified by bits CCP1M<3:0> (CCP1CON<3:0>). Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 11-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
FIGURE 11-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCP1IF (PIR1<5>)
EXAMPLE 11-1:
CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
Prescaler / 1, 4, 16 GP2/CCP1 pin
CCPR1H and Edge Detect Capture Enable TMR1H CCP1CON<3:0> Q's
CCPR1L
MOVWF
CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCP1CON ;Load CCP1CON with this ;value
TMR1L
DS41211B-page 70
Preliminary
2004 Microchip Technology Inc.
PIC12F683
11.2 Compare Mode
11.2.1 CCP1 PIN CONFIGURATION
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the GP2/AN2/T0CKI/INT/ COUT/CCP1 pin is: * Driven high * Driven low * Remains unchanged The action on the pin is based on the value of control bits, CCP1M<3:0> (CCP1CON<3:0>). At the same time, interrupt flag bit, CCP1IF (PIR1<5>), is set. The user must configure the GP2/AN2/T0CKI/INT/ COUT/CCP1 pin as an output by clearing the TRISIO<2> bit. Note: Clearing the CCP1CON register will force the GP2/AN2/T0CKI/INT/COUT/ CCP1 compare output latch to the default low level. This is not the GPIO data latch.
11.2.2
TIMER1 MODE SELECTION
FIGURE 11-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCP1CON<3:0> Mode Select Set Flag bit CCP1IF (PIR1<5>) CCPR1H CCPR1L
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
11.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1 pin is not affected. The CCP1IF (PIR1<5>) bit is set, causing a CCP interrupt (if enabled). See Register 11-1.
GP2/CCP1 pin Q S R TRISIO<2> Output Enable
11.2.4
SPECIAL EVENT TRIGGER
Output Logic
Match
Comparator TMR1H TMR1L
In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair and starts A/D conversion, if enabled. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. Note: The special event trigger from the CCP1 modules will not set interrupt flag bit TMR1IF (PIR1<0>).
Special Event Trigger Special Event Trigger will: * Clear TMR1H and TMR1L registers * NOT set interrupt flag bit TMR1F (PIR1<0>) * Set the GO/DONE bit (ADCON0<1>)
TABLE 11-2:
Addr 0Bh/ 8Bh 0Ch 0Eh 0Fh 10h 1Ah 13h 14h 15h 8Ch Name INTCON PIR1 TMR1L TMR1H T1CON CMCON1 CCPR1L CCPR1H CCP1CON PIE1
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Bit 7 GIE EEIF Bit 6 PEIE ADIF Bit 5 T0IE CCP1IF Bit 4 INTE -- Bit 3 GPIE CMIF Bit 2 T0IF OSFIF Bit 1 INTF TMR2IF Bit 0 GPIF Value on POR, BOD Value on all other Resets
0000 0000 0000 0000
TMR1IF 000- 0000 000- 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- -- -- -- -- --
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu T1GSS CMSYNC ---- --10 ---- --10 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte -- EEIE -- ADIE DC1B1 CCP1IE DC1B0 -- CMIE
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
Legend:
-- = unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare or Timer1 module.
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 71
PIC12F683
11.3 PWM Mode (PWM)
FIGURE 11-4:
Period
PWM OUTPUT
In Pulse Width Modulation mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the GPIO data latch, the TRISIO<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the GPIO data latch.
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
Figure 11-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 11.3.3 "Setup for PWM Operation".
11.3.1
PWM PERIOD
FIGURE 11-3:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula.
EQUATION 11-1:
PWM Period = [(PR2) + 1] * 4 * Tosc * TMR2 Prescale Value
Duty Cycle Registers CCPR1L
PWM frequency is defined as 1/[PWM period].
CCPR1H (Slave) GP2/CCP1 Comparator R Q
When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared. * The CCP1 pin is set (Exception: If PWM duty cycle = 0%, the CCP1 pin will not be set). * The PWM duty cycle is latched from CCPR1L into CCPR1H. Note: The Timer2 postscaler (see Section 7.1 "Timer2 Operation") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
TMR2
(Note 1) S
Comparator Clear Timer, CCP1 pin and latch D.C.
TRISIO<2>
PR2
Note 1: The 8-bit timer is concatenated with 2-bit internal Q clock, or 2 bits of the prescaler, to create 10-bit time base.
A PWM output (Figure 11-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
DS41211B-page 72
Preliminary
2004 Microchip Technology Inc.
PIC12F683
11.3.2 PWM DUTY CYCLE EQUATION 11-3:
log Resolution = FOSC FPWM * TMR2 Prescale Value log(2)
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time.
bits
Note:
If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.
EQUATION 11-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4> * TOSC * TMR2 Prescale Value
11.3.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring the CCP1 module for PWM operation: 1. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISIO<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. Note: The PWM module may generate a premature pulse when changing the duty cycle. For sensitive applications, disable the PWM module prior to modifying the duty cycle.
CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitch-free PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following formula.
2. 3. 4. 5.
TABLE 11-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
1.22 kHz 16 0xFFh 10 4.88 kHz 4 0xFFh 10 19.53 kHz 1 0xFFh 10 78.12 kHz 1 0x3Fh 8 156.3 kHz 1 0x1Fh 7 208.3 kHz 1 0x17h 6.6
PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 73
PIC12F683
TABLE 11-4:
Addr Name
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 GIE EEIF -- Bit 6 PEIE ADIF Bit 5 T0IE CCP1IF Bit 4 INTE -- Bit 3 GPIE CMIF Bit 2 T0IF OSFIF Bit 1 INTF TMR2IF Bit 0 GPIF Value on POR, BOD Value on all other Resets
0Bh/ INTCON 8Bh 0Ch 11h 12h 13h 14h 15h 8Ch 92h PIR1 TMR2 T2CON CCPR1L CCPR1H CCP1CON PIE1 PR2
0000 0000 0000 0000
TMR1IF 000- 0000 000- 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Timer2 Module Register Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte -- EEIE -- ADIE DC1B1 CCP1IE DC1B0 -- CCP1M3 CMIE OSFIE TMR2IE
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 TMR1IE 000- 0000 000- 0000 1111 1111 1111 1111
Timer2 Module Period Register -- = unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the PWM or Timer2 module.
Legend:
DS41211B-page 74
Preliminary
2004 Microchip Technology Inc.
PIC12F683
12.0 SPECIAL FEATURES OF THE CPU
The PIC12F683 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power-up Timer to provide at least a 64 ms Reset. With these three functions on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-down mode. The user can wake-up from Sleep through: * External Reset * Watchdog Timer Wake-up * An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options (see Register 12-1).
The PIC12F683 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Detect (BOD) * Interrupts * Watchdog Timer (WDT) * Oscillator Selection * Sleep * Code Protection * ID Locations * In-Circuit Serial Programming
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Preliminary
DS41211B-page 75
PIC12F683
12.1 Configuration Bits
Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information. The configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1') to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h.
REGISTER 12-1:
-- bit 13 bit 13-12 bit 11 --
CONFIG - CONFIGURATION WORD (ADDRESS: 2007h)
IESO BODEN1 BODEN0 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 0
FCMEN
Unimplemented: Read as `1' FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled 0 = Internal External Switchover mode is disabled BODEN<1:0>: Brown-out Detect Selection bits(1) 11 = BOD enabled 10 = BOD enabled during operation and disabled in Sleep 01 = BOD controlled by SBODEN bit (PCON<4>) 00 = BOD disabled CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled MCLRE: GP3/MCLR pin function select bit(4) 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital input, MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>) FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 110 = RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN Note 1: 2: 3: Enabling Brown-out Detect does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off. The entire program memory will be erased when the code protection is turned off. When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
DS41211B-page 76
Preliminary
2004 Microchip Technology Inc.
PIC12F683
12.2 Calibration Bits
The Brown-out Detect (BOD), Power-on Reset (POR) and 8 MHz internal oscillator (HFINTOSC) are factory calibrated. These calibration values are stored in the Calibration Word register, as shown in Register 12-2 and are mapped in program memory location 2008h. The Calibration Word register is not erased when the device is erased when using the procedure described in the "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204). Therefore, it is not necessary to store and reprogram these values when the device is erased. Note: Address 2008h is beyond the user program memory space. It belongs to the special configuration memory space (2000h3FFFh), which can be accessed only during programming. See "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information.
REGISTER 12-2:
-- bit 13 bit 13 bit 12-6 FCAL6 FCAL5
CALIB - CALIBRATION WORD (ADDRESS: 2008h)
FCAL4 FCAL3 FCAL2 FCAL1 FCAL0 -- POR1 POR0 BOD2 BOD1 BOD0 bit 0
Unimplemented: Read as `0' FCAL<6:0>: Internal Oscillator Calibration bits 0111111 = Maximum frequency . . 0000001 0000000 = Center frequency 1111111 . . 1000000 = Minimum frequency Unimplemented: Read as `0' POR<1:0>: POR Calibration bits 00 = Lowest POR voltage 11 = Highest POR voltage BOD<2:0>: BOD Calibration bits 000 = Reserved 001 = Lowest BOD voltage 111 = Highest BOD voltage
bit 5 bit 4-3
bit 2-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 77
PIC12F683
12.3 Reset
The PIC12F683 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Detect (BOD) They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 12-2. These bits are used in software to determine the nature of the Reset. See Table 12-4 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 12-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 15.0 "Electrical Specifications" for pulse width specifications.
Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on: * * * * * Power-on Reset MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Detect (BOD)
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/VPP pin SLEEP WDT Module VDD Rise Detect VDD Brown-out(1) Detect Power-on Reset BODEN SBODEN WDT Time-out Reset
S
OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKI pin PWRT LFINTOSC 11-bit Ripple Counter R Q Chip_Reset
Enable PWRT Enable OST
Note 1: Refer to the Configuration Word register (Register 12-1).
DS41211B-page 78
Preliminary
2004 Microchip Technology Inc.
PIC12F683
12.3.1 POWER-ON RESET FIGURE 12-2:
VDD
The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 15.0 "Electrical Specifications" for details. If the BOD is enabled, the maximum rise time specification does not apply. The BOD circuitry will keep the device in Reset until VDD reaches VBOD (see Section 12.3.4 "Brown-out Detect (BOD)"). Note: The POR circuit does not produce an internal Reset when VDD declines. To re-enable the POR, VDD must reach Vss for a minimum of 100 s.
RECOMMENDED MCLR CIRCUIT
PIC12F683
R1 1 k (or greater) MCLR C1 0.1 F (optional, not critical)
12.3.3
POWER-UP TIMER (PWRT)
When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to the Application Note AN607, "Power-up Trouble Shooting" (DS00607).
12.3.2
MCLR
The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Detect. The Power-up Timer operates from the 31 kHz LFINTOSC oscillator. For more information, see Section 3.4 "Internal Clock Modes". The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Detect is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip and vary due to: * VDD variation * Temperature variation * Process variation See DC parameters for details (Section 15.0 "Electrical Specifications").
PIC12F683 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from early devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 12-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When cleared, MCLR is internally tied to VDD and an internal weak pull-up is enabled for the MCLR pin. In-Circuit Serial Programming is not affected by selecting the internal MCLR option.
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Preliminary
DS41211B-page 79
PIC12F683
12.3.4 BROWN-OUT DETECT (BOD)
The BODEN0 and BODEN1 bits in the Configuration Word register select one of four BOD modes. Two modes have been added to allow software or hardware control of the BOD enable. When BODEN<1:0> = 01, the SBODEN bit (PCON<4>) enables/disables the BOD allowing it to be controlled in software. By selecting BODEN<1:0>, the BOD is automatically disabled in Sleep to conserve power and enabled on wake-up. In this mode, the SBODEN bit is disabled. See Register 12-1 for the Configuration Word register definition. If VDD falls below VBOD for greater than parameter TBOD (see Section 15.0 "Electrical Specifications"), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not ensured to occur if VDD falls below VBOD for less than parameter (TBOD). On any Reset (Power-on, Brown-out Detect, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises above VBOD (see Figure 12-3). The Power-up Timer will now be invoked, if enabled and will keep the chip in Reset an additional 64 ms. Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word register. If VDD drops below VBOD while the Power-up Timer is running, the chip will go back into a Brown-out Detect and the Power-up Timer will be re-initialized. Once VDD rises above VBOD, the Power-up Timer will execute a 64 ms Reset.
12.3.4.1
BOD Calibration
The PIC12F683 stores the BOD calibration values in fuses located in the Calibration Word register (2008h). The Calibration Word register is not erased when using the specified bulk erase sequence in the "PIC12F6XX/ 16F6XX Memory Programming Specification" (DS41204) and thus, does not require reprogramming. Note: Address 2008h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information.
FIGURE 12-3:
BROWN-OUT SITUATIONS
VDD VBOD
Internal Reset VDD
64 ms(1)
VBOD < 64 ms
Internal Reset
64 ms(1)
VDD
VBOD
Internal Reset Note 1:
64 ms(1) 64 ms delay only if PWRTE bit is programmed to `0'.
DS41211B-page 80
Preliminary
2004 Microchip Technology Inc.
PIC12F683
12.3.5 TIME-OUT SEQUENCE 12.3.6
On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 12-4, Figure 12-5 and Figure 12-6 depict time-out sequences. The device can execute code from the INTOSC while OST is active by enabling Two-Speed Start-up or Fail-Safe Monitor (see Section 3.6 "Two-Speed Clock Start-up Mode" and Section 3.7 "Fail-Safe Clock Monitor"). Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F683 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers.
POWER CONTROL (PCON) REGISTER
The Power Control register PCON (address 8Eh) has two status bits to indicate what type of Reset that last occurred. Bit 0 is BOD (Brown-out). BOD is unknown on Poweron Reset. It must then be set by the user and checked on subsequent Resets to see if BOD = 0, indicating that a Brown-out has occurred. The BOD status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (BODEN<1:0> = 00 in the Configuration Word register). Bit 1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent Reset, if POR is `0', it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 4.2.3 "Ultra LowPower Wake-up" and Section 12.3.4 "Brown-out Detect (BOD)".
TABLE 12-1:
Oscillator Configuration XT, HS, LP
TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC -- Brown-out Detect PWRTE = 0 TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC -- Wake-up from Sleep 1024 * TOSC --
RC, EC, INTOSC
TABLE 12-2:
POR 0 1 u u u u u 0 u u u u
PCON BITS AND THEIR SIGNIFICANCE
TO 1 1 0 0 u 1 PD 1 1 u 0 u 0 Power-on Reset Brown-out Detect WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep Condition
BOD
Legend: u = unchanged, x = unknown
TABLE 12-3:
Address 03h 8Eh Legend: Note 1: Name
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Bit 7 IRP -- Bit 6 RP1 -- Bit 5 RPO Bit 4 TO Bit 3 PD -- Bit 2 Z -- Bit 1 DC POR Bit 0 C BOD Value on POR, BOD 0001 1xxx --01 --qq Value on all other Resets(1) 000q quuu --0u --uu
STATUS PCON
ULPWUE SBODEN
u = unchanged, x = unknown, -- = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by BOD. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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Preliminary
DS41211B-page 81
PIC12F683
FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD MCLR Internal POR TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-6:
VDD MCLR Internal POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
DS41211B-page 82
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2004 Microchip Technology Inc.
PIC12F683
TABLE 12-4:
Register
INITIALIZATION CONDITION FOR REGISTERS
Address Power-on Reset MCLR Reset WDT Reset Brown-out Detect(1) uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu --00 0000 ---0 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 -000 0000 uuuu uuuu uuuu uuuu 0000 0000 ---0 1000 0000 0000 ---- --10 uuuu uuuu 00-- 0000 1111 1111 --11 1111 0000 0000 --0u --uu -110 x000 ---u uuuu 1111 1111 --11 -111 --00 0000 0-0- 0000 0000 0000 0000 0000
(1,5)
Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu --uu uuuu ---u uuuu uuuu uuuu(2) uuuu uuuu(2) uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu ---- --uu uuuu uuuu uu-- uuuu uuuu uuuu --uu uuuu uuuu uuuu --uu --uu -uuu uuuu ---u uuuu 1111 1111 uuuu uuuu --uu uuuu u-u- uuuu uuuu uuuu uuuu uuuu
W INDF TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON WDTCON CMCON0 CMCON1 ADRESH ADCON0 OPTION_REG TRISIO PIE1 PCON OSCCON OSCTUNE PR2 WPU IOC VRCON EEDAT EEADR Legend: Note 1: 2: 3: 4: 5:
-- 00h/80h 01h 02h/82h 03h/83h 04h/84h 05h 0Ah/8Ah 0Bh/8Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h 14h 15h 18h 19h 20h 1Eh 1Fh 81h 85h 8Ch 8Eh 8Fh 90h 92h 95h 96h 99h 9Ah 9Bh
xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx xx00 ---0 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 -000 0000 xxxx xxxx xxxx xxxx 0000 0000 ---0 1000 0000 0000 ---- --10 xxxx xxxx 00-- 0000 1111 1111 --11 1111 0000 0000 --01 --0x -110 x000 ---0 0000 1111 1111 --11 -111 --00 0000 0-0- 0000 0000 0000 0000 0000
u = unchanged, x = unknown, -- = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 12-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
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Preliminary
DS41211B-page 83
PIC12F683
TABLE 12-4:
Register
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Address Power-on Reset MCLR Reset WDT Reset Brown-out Detect(1) ---- q000 ---- ---uuuu uuuu 1111 1111 Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out ---- uuuu ---- ---uuuu uuuu uuuu uuuu
EECON1 EECON2 ADRESL ANSEL Legend: Note 1: 2: 3: 4: 5:
9Ch 9Dh 9Eh 9Fh
---- x000 ---- ---xxxx xxxx 1111 1111
u = unchanged, x = unknown, -- = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 12-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
TABLE 12-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1
(1)
Status Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1uuu uuu1 0uuu
PCON Register --01 --0x --0u --uu --0u --uu --0u --uu --uu --uu --01 --10 --uu --uu
Power-on Reset MCLR Reset during Normal Operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Detect Interrupt Wake-up from Sleep
Legend: u = unchanged, x = unknown, -- = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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PIC12F683
12.4
* * * * * * * * * *
Interrupts
The PIC12F683 has 11 sources of interrupt: External Interrupt GP2/INT TMR0 Overflow Interrupt GPIO Change Interrupts 2 Comparator Interrupts A/D Interrupt Timer1 Overflow Interrupt Timer2 Match Interrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt CCP Interrupt
For external interrupt events, such as the INT pin or GPIO change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 12-8). The latency is the same for one or twocycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. For additional information on Timer1, Timer2, comparators, A/D, data EEPROM or CCP modules, refer to the respective peripheral section.
The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. A Global Interrupt Enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIE1 register. GIE is cleared on Reset. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: * INT Pin Interrupt * GPIO Change Interrupt * TMR0 Overflow Interrupt The peripheral interrupt flags are contained in the special register, PIR1. The corresponding interrupt enable bit is contained in special register, PIE1. The following interrupt flags are contained in the PIR1 register: * * * * * * * EEPROM Data Write Interrupt A/D Interrupt 2 Comparator Interrupts Timer1 Overflow Interrupt Timer 2 Match Interrupt Fail-Safe Clock Monitor Interrupt CCP Interrupt
12.4.1
GP2/INT INTERRUPT
External interrupt on GP2/INT pin is edge-triggered; either rising if the INTEDG bit (OPTION<6>) is set, or falling if the INTEDG bit is clear. When a valid edge appears on the GP2/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The GP2/INT interrupt can wake-up the processor from Sleep if the INTE bit was set prior to going into Sleep. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). See Section 12.7 "Power-Down Mode (Sleep)" for details on Sleep and Figure 12-10 for timing of wake-up from Sleep through GP2/INT interrupt. Note: The ANSEL (91h) and CMCON0 (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
When an interrupt is serviced: * The GIE is cleared to disable any further interrupt. * The return address is pushed onto the stack. * The PC is loaded with 0004h.
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Preliminary
DS41211B-page 85
PIC12F683
12.4.2 TMR0 INTERRUPT 12.4.3 GPIO INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. See Section 5.0 "Timer0 Module" for operation of the Timer0 module. An input change on GPIO change sets the GPIF (INTCON<0>) bit. The interrupt can be enabled/ disabled by setting/clearing the GPIE (INTCON<3>) bit. Plus, individual pins can be configured through the IOC register. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the GPIF interrupt flag may not get set.
FIGURE 12-7:
INTERRUPT LOGIC
IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR2IF TMR2IE TMR1IF TMR1IE CMIF CMIE ADIF ADIE EEIF EEIE OSFIF OSFIE CCP1IF CCP1IE T0IF T0IE INTF INTE GPIF GPIE PEIE GIE Wake-up (If in Sleep mode)
Interrupt to CPU
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Preliminary
2004 Microchip Technology Inc.
PIC12F683
FIGURE 12-8:
Q1 OSC1 CLKOUT(3)
(4)
INT PIN INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5:
(1) (5)
(1)
Interrupt Latency(2)
PC Inst (PC) Inst (PC - 1)
PC + 1 Inst (PC + 1) Inst (PC)
PC + 1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKOUT is available only in INTOSC and RC Oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 15.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 12-6:
Address Name
SUMMARY OF INTERRUPT REGISTERS
Bit 7 GIE EEIF EEIE Bit 6 PEIE ADIF ADIE Bit 5 T0IE CCP1IF CCP1IE Bit 4 INTE -- -- Bit 3 GPIE CMIF CMIE Bit 2 T0IF OSFIF OSFIE Bit 1 INTF Bit 0 GPIF Value on POR, BOD Value on all other Resets
0Bh, 8Bh INTCON 0Ch 8Ch Legend: PIR1 PIE1
0000 0000 0000 0000
TMR2IF TMR1IF 000- 0000 000- 0000 TMR2IE TMR1IE 000- 0000 000- 0000
x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by the interrupt module.
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Preliminary
DS41211B-page 87
PIC12F683
12.5 Context Saving During Interrupts
Note: The PIC12F683 normally does not require saving the PCLATH. However, if computed GOTOs are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR. During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and Status registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC12F683 (see Figure 2-2), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, makes it easier to context save and restore. The same code shown in Example 12-1 can be used to: * * * * * Store the W register. Store the Status register. Execute the ISR code. Restore the Status (and Bank Select Bit register). Restore the W register.
EXAMPLE 12-1:
MOVWF SWAPF CLRF MOVWF : :(ISR) : SWAPF MOVWF SWAPF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
;Copy ;Swap ;bank ;Save W to TEMP register status to be saved into W 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register
W_TEMP STATUS,W STATUS STATUS_TEMP
;Insert user code here STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into Status register ;Swap W_TEMP ;Swap W_TEMP into W
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Preliminary
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PIC12F683
12.6 Watchdog Timer (WDT)
For PIC12F683, the WDT has been modified from previous PIC12F683 devices. The new WDT is code and functionally compatible with previous PIC12F683 WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaler value for the WDT and TMR0 at the same time. In addition, the WDT time-out value can be extended to 268 seconds. WDT is cleared under certain conditions described in Table 12-7. A new prescaler has been added to the path between the INTRC and the multiplexers used to select the path for the WDT. This prescaler is 16 bits and can be programmed to divide the INTRC by 128 to 65536, giving the time base used for the WDT a nominal range of 1 ms to 268s.
12.6.2
WDT CONTROL
The WDTE bit is located in the Configuration Word register. When set, the WDT runs continuously. When the WDTE bit in the Configuration Word register is set, the SWDTEN bit (WDTCON<0>) has no effect. If WDTE is clear, then the SWDTEN bit can be used to enable and disable the WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits (OPTION_REG) have the same function as in previous versions of the PIC12F683 family of microcontrollers. See Section 5.0 "Timer0 Module" for more information.
12.6.1
WDT OSCILLATOR
The WDT derives its time base from the 31 kHz LFINTOSC. The LTS bit does not reflect that the LFINTOSC is enabled. The value of WDTCON is `---0 1000' on all Resets. This gives a nominal time base of 16 ms, which is compatible with the time base generated with previous PIC12F683 microcontroller versions. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled).
FIGURE 12-9:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source 0 Prescaler(1) 16-bit WDT Prescaler 1 8 PSA
PS<2:0> To TMR0 0 1 PSA
31 kHz LFINTOSC Clock
WDTPS<3:0>
WDTE from Configuration Word register SWDTEN from WDTCON WDT Time-out
Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 "Prescaler" for more information.
TABLE 12-7:
WDTE = 0
WDT STATUS
Conditions WDT
CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP
Cleared
Cleared until the end of OST
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DS41211B-page 89
PIC12F683
REGISTER 12-3: WDTCON - WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h)
U-0 -- bit 7 bit 7-5 bit 4-1 Unimplemented: Read as `0' WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved SWDTEN: Software Enable or Disable the Watchdog Timer(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE configuration bit = 0, then it is possible to turn WDT on/off with this control bit. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 WDTPS3 R/W-1 WDTPS2 R/W-0 WDTPS1 R/W-0 WDTPS0 R/W-0 SWDTEN bit 0
bit 0
TABLE 12-8:
Address 18h 81h 2007h
(1)
SUMMARY OF WATCHDOG TIMER REGISTERS
Name Bit 7 -- GPPU CPD Bit 6 -- INTEDG CP Bit 5 -- T0CS MCLRE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN T0SE PWRTE PSA WDTE PS2 FOSC2 PS1 FOSC1 PS0 FOSC0
WDTCON OPTION_REG CONFIG
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of all Configuration Word register bits.
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PIC12F683
12.7 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: * * * * * WDT will be cleared but keeps running. PD bit in the Status register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). Other peripherals cannot generate interrupts, since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed.
For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin and the comparators and CVREF should be disabled. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on GPIO should be considered. The MCLR pin must be at a logic high level. Note: It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low.
The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.
12.7.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
12.7.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from GP2/INT pin, GPIO change or a peripheral interrupt.
The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the Status register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. 6. 7. 8. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. ECCP Capture mode interrupt. Special event trigger (Timer1 in Asynchronous mode using an external clock). A/D conversion (when A/D clock source is RC). EEPROM write operation completion. Comparator output changes state. Interrupt-on-change. External Interrupt from INT pin.
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Preliminary
DS41211B-page 91
PIC12F683
FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC Processor in Sleep Interrupt Latency (3)
PC Instruction Inst(PC) = Sleep Fetched Instruction Inst(PC - 1) Executed 1: 2: 3: 4:
PC + 1 Inst(PC + 1) Sleep
PC + 2
PC + 2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy Cycle
Dummy Cycle
Note
XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RCIO Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
12.8
Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP for verification purposes. Note: The entire data EEPROM and Flash program memory will be erased when the code protection is turned off. See the PIC12F6XX/16F6XX Memory Programming Specification (DS41204) for more information.
This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the GP0 and GP1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the "PIC12F6XX/ 16F6XX Memory Programming Specification" (DS41204) for more information. GP0 becomes the programming data and GP1 becomes the programming clock. Both GP0 and GP1 are Schmitt Trigger inputs in this mode. After Reset, to place the device into Program/Verify mode, the Program Counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. For complete details of serial programming, please refer to the "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204). A typical In-Circuit Serial Programming connection is shown in Figure 12-11.
12.9
ID Locations
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used.
12.10 In-Circuit Serial Programming
The PIC12F683 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for: * Power * Ground * Programming Voltage
DS41211B-page 92
Preliminary
2004 Microchip Technology Inc.
PIC12F683
FIGURE 12-11: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections External Connector Signals +5V 0V
VPP
When the ICD pin on the PIC12F683 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 12-9 shows which features are consumed by the background debugger:
*
PIC12F683
TABLE 12-9:
VDD VSS
DEBUGGER RESOURCES
Description ICDCLK, ICDDATA 1 level Address 0h must be NOP 700h-7FFh
Resource I/O pins Stack Program Memory
MCLR/VPP/GP3 GP1 GP0
CLK Data I/O
For more information, see "MPLAB ICD 2 In-Circuit Debugger User's Guide" (DS51331), available on Microchip's web site (www.microchip.com). * * *
FIGURE 12-12:
To Normal Connections *Isolation devices (as required).
14-PIN ICD PINOUT
14-Pin PDIP In-Circuit Debug Device
NC ICDMCLR/VPP VDD GP5 GP4 GP3 ICD
1 2 3 4 5 6 7 14 13 12 11 10 9 8
12.11 In-Circuit Debugger
Since in-circuit debugging requires the loss of clock, data and MCLR pins, MPLAB(R) ICD 2 development with an 8-pin device is not practical. A special 14-pin PIC12F683 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. A special debugging adapter allows the ICD device to be used in place of a PIC12F683 device. The debugging adapter is the only source of the ICD device.
ICDCLK ICDDATA Vss GP0 GP1 GP2 NC
PIC12F683-ICD
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NOTES:
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13.0 INSTRUCTION SET SUMMARY
The PIC12F683 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 13-1, while the various opcode fields are summarized in Table 13-1. Table 13-2 lists the instructions recognized by the MPASMTM Assembler. A complete description of each instruction is also available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023). For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. Note: To maintain upward compatibility with future products, do not use the OPTION and TRIS instructions. For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO. This example would have the unintended result of clearing the condition that set the GPIF flag.
TABLE 13-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit
d
PC TO PD
FIGURE 13-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
0
All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
0
13.1
READ-MODIFY-WRITE OPERATIONS
0
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified and the result is stored according to either the instruction or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register.
k = 11-bit immediate value
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TABLE 13-2:
Mnemonic, Operands
PIC12F683 INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C, DC, Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C, DC, Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b k k k k k k k k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C, DC, Z Z TO, PD Z 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO, PD C, DC, Z Z
2: 3:
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
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13.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
BTFSC Syntax: Operands: Operation: Description:
Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 If bit `b' in register `f' is `1', the next instruction is executed. If bit `b' in register `f' is `0', the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction.
Status Affected: None
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BTFSS Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction.
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CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 k 2047 (PC) + 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Call subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: None Description: Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff
The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' = 0, destination is W register. If `d' = 1, the destination is file register `f' itself. `d' = 1 is useful to test a file register since status flag Z is affected. 1 1 MOVF FSR, 0 After Instruction
W = value in FSR register Z =1
Words: INCF Syntax: Operands: Operation: Status Affected: Description: Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. Cycles: Example:
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MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Move Literal to W [ label ] k (W) None
11 00xx kkkk kkkk
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
MOVLW k
0 k 255
The eight-bit literal `k' is loaded into the W register. The don't cares will assemble as `0's. 1 1
MOVLW 0x5A
Words: Cycles: Example:
After Instruction W=
0x5A IORWF f Syntax: Operands: Operation: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
MOVWF Syntax: Operands: Operation: Encoding: Description: Words: Cycles: Example:
Move W to f [ label ] (W) (f)
00 0000 1fff ffff
MOVWF
0 f 127
Status Affected: None Move data from W register to register `f'. 1 1
MOVWF OPTION
Status Affected: Description:
Before Instruction OPTION = W = After Instruction OPTION = W = NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example: 1 1
NOP
0xFF 0x4F 0x4F 0x4F RETFIE Syntax: Operands: Operation:
0xx0 0000
No Operation [ label ] None No operation None
00 0000
Return from Interrupt [ label ] None TOS PC, 1 GIE
00 0000 0000 1001
NOP
RETFIE
Status Affected: None Encoding: Description: Return from interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE
No operation.
Words: Cycles: Example:
After Interrupt PC = GIE =
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RETLW Syntax: Operands: Operation: Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC
11 01xx kkkk kkkk
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Left f through Carry [ label ] RLF f,d 0 f 127 d [0,1] See description below C
00 1101 dfff ffff
Status Affected: None Encoding: Description: The W register is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2
CALL TABLE;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table
Words: Cycles: Example:
The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'.
C Register f
Words: Cycles: Example:
1 1
RLF REG1,0
Before Instruction W = 0x07 After Instruction W = value of k8
Before Instruction REG1 = C = After Instruction REG1 = W = C =
1110 0110 0 1110 0110 1100 1100 1
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
C Register f
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SLEEP Syntax: Operands: Operation: [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The Power-down status bit, PD, is cleared. Time-out status bit, TO, is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. SWAPF Syntax: Operands: Operation: Status Affected: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'.
Status Affected: Description:
SUBLW Syntax: Operands: Operation: Description:
Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register.
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
Status Affected: C, DC, Z
SUBWF Syntax: Operands: Operation: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
XORWF Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
Status Affected: C, DC, Z
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14.0 DEVELOPMENT SUPPORT
14.1
The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB C30 C Compiler - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator - MPLAB dsPIC30 Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 4 Demonstration Board - PICDEM 17 Demonstration Board - PICDEM 18R Demonstration Board - PICDEM LIN Demonstration Board - PICDEM USB Demonstration Board * Evaluation Kits - KEELOQ(R) - PICDEM MSC - microID(R) - CAN - PowerSmart(R) - Analog
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor with color coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Extensive on-line help The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files (assembly or C) - mixed assembly and C - machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increasing flexibility and power.
14.2
MPASM Assembler
The MPASM assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects * User defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
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14.3 MPLAB C17 and MPLAB C18 C Compilers 14.6 MPLAB ASM30 Assembler, Linker and Librarian
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 compiler uses the assembler to produce it's object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
14.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB object librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
14.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until Break or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers, as well as the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool.
14.5
MPLAB C30 C Compiler
14.8
MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI compliant, optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source. The compiler also supports many command line options and language extensions to take full advantage of the dsPIC30F device hardware capabilities and afford fine control of the compiler code generator. MPLAB C30 is distributed with a complete ANSI C standard library. All library functions have been validated and conform to the ANSI C library standard. The library includes functions for string manipulation, dynamic memory allocation, data conversion, timekeeping and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high-level source debugging with the MPLAB IDE.
The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines.
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14.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator 14.11 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro microcontrollers. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost effective in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real-time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices.
The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
14.12 PRO MATE II Universal Device Programmer
The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the PRO MATE II device programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode.
14.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICD 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, up to 2 Mb of emulation memory and the ability to view variables in real-time. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
14.13 MPLAB PM3 Device Programmer
The MPLAB PM3 is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In StandAlone mode, the MPLAB PM3 device programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode. MPLAB PM3 connects to the host PC via an RS-232 or USB cable. MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
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14.14 PICSTART Plus Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
14.17 PICDEM 2 Plus Demonstration Board
The PICDEM 2 Plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or MPLAB ICD 2 with a Universal Programmer Adapter. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2 x 16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs and sample PIC18F452 and PIC16F877 Flash microcontrollers.
14.15 PICDEM 1 PICmicro Demonstration Board
The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device programmer or a PICSTART Plus development programmer. The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional application components. Features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs.
14.18 PICDEM 3 PIC16C92X Demonstration Board
The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package. All the necessary hardware and software is included to run the demonstration programs.
14.19 PICDEM 4 8/14/18-Pin Demonstration Board
The PICDEM 4 can be used to demonstrate the capabilities of the 8, 14 and 18-pin PIC16XXXX and PIC18XXXX MCUs, including the PIC16F818/819, PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to showcase the many features of these low pin count parts, including LIN and Motor Control using ECCP. Special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow onboard hardware to be disabled to eliminate current draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, DB-9 RS-232 interface, ICD connector for programming via ICSP and development with MPLAB ICD 2, 2 x 16 liquid crystal display, PCB footprints for H-Bridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User's Guide.
14.16 PICDEM.net Internet/Ethernet Demonstration Board
The PICDEM.net demonstration board is an Internet/ Ethernet demonstration board using the PIC18F452 microcontroller and TCP/IP firmware. The board supports any 40-pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452. This kit features a user friendly TCP/IP stack, web server with HTML, a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface and a 16 x 2 LCD display. Also included is the book and CD-ROM "TCP/IP Lean, Web Servers for Embedded Systems," by Jeremy Bentham
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14.20 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. A generous prototype area is available for user hardware expansion.
14.24 PICDEM USB PIC16C7X5 Demonstration Board
The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. This board provides the basis for future USB products.
14.25 Evaluation and Programming Tools
In addition to the PICDEM series of circuits, Microchip has a line of evaluation kits and demonstration software for these products. * KEELOQ evaluation and programming tools for Microchip's HCS Secure Data Products * CAN developers kit for automotive network applications * Analog design boards and filter design software * PowerSmart battery charging evaluation/ calibration kits * IrDA(R) development kit * microID development and rfLabTM development software * SEEVAL(R) designer kit for memory evaluation and endurance calculations * PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits.
14.21 PICDEM 18R PIC18C601/801 Demonstration Board
The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/Demultiplexed and 16-bit Memory modes. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801.
14.22 PICDEM LIN PIC16C43X Demonstration Board
The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on-board LIN transceivers. A PIC16F874 Flash microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus communication.
14.23 PICkitTM 1 Flash Starter Kit
A complete "development system in a box", the PICkit Flash Starter Kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin Flash PIC(R) microcontrollers. Powered via USB, the board operates under a simple Windows GUI. The PICkit 1 Starter Kit includes the User's Guide (on CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB(R) IDE (Integrated Development Environment) software, software and hardware "Tips 'n Tricks for 8-pin Flash PIC(R) Microcontrollers" Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices.
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15.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings()
Ambient temperature under bias....................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ..................................................................................................................... 300 mA Maximum current into VDD pin ........................................................................................................................ 250 mA Input clamp current, IIK (VI < 0 or VI > VDD)............................................................................................................... 20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)......................................................................................................... 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by GPIO ..................................................................................................................... 200 mA Maximum current sourced GPIO..................................................................................................................... 200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling this pin directly to VSS.
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FIGURE 15-1:
5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20
PIC12F683 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
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15.1 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No. D001 D001C D001D D002 D003 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Detect
Sym VDD
Characteristic Supply Voltage
2.0 3.0 4.5 1.5* --
-- -- -- -- VSS
5.5 5.5 5.5 -- --
V V V V V
FOSC < = 4 MHz FOSC < = 10 MHz FOSC < = 20 MHz Device in Sleep mode See Section 12.3.1 "Power-on Reset" for details
D004
SVDD
0.05*
--
--
V/ms See Section 12.3.1 "Power-on Reset" for details V
D005
VBOD
--
2.1
--
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
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15.2 DC Characteristics: PIC12F683-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Min -- -- -- D011 -- -- -- D012 -- -- -- D013 -- -- -- D014 -- -- -- D015 -- -- -- D016 -- -- -- D017 -- -- -- D018 -- -- Typ 9 18 35 110 190 330 220 370 0.6 70 140 260 180 320 580 10 25 40 340 500 0.8 250 375 750 3.0 3.7 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD A A A A A A A A A A A A A A A A A A A A mA A A A mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode FOSC = 4 MHz INTOSC mode FOSC = 31 kHz INTRC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32 kHz LP Oscillator mode DC CHARACTERISTICS Param No. D010 Device Characteristics Supply Current(1,2)
Sym IDD
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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15.2 DC Characteristics: PIC12F683-I (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Min -- -- -- D021 -- -- -- D022 D023 -- -- -- -- -- D024 -- -- -- D025 -- -- -- D026 -- -- Typ 0.00099 0.0012 0.0029 1.8 2.7 8.4 58 109 18 28 60 58 85 138 7.0 8.6 10 1.2 0.0029 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD N/A N/A N/A A A A A A A A A A A A A A A nA A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current(3) T1OSC Current(3) CVREF Current(3) Comparator Current(3) BOD Current(3) WDT Current(3) Note WDT, BOD, Comparator, VREF and T1OSC disabled DC CHARACTERISTICS Param No. D020 Device Characteristics Power-down Base Current(4)
Sym IPD
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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15.3 DC Characteristics: PIC12F683-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Min -- -- -- D011E -- -- -- D012E -- -- -- D013E -- -- -- D014E -- -- -- D015E -- -- -- D016E -- -- -- D017E -- -- -- D018E -- -- Typ 9 18 35 110 190 330 220 370 0.6 70 140 260 180 320 580 10 25 40 340 500 0.8 250 375 750 3.0 3.7 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD A A A A A A A A mA A A A A A A A A A A A mA A A A mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode FOSC = 4 MHz INTOSC mode FOSC = 31 kHz INTRC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32 kHz LP Oscillator mode DC CHARACTERISTICS Param No. Device Characteristics Supply Current(1,2)
Sym
D010E IDD
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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15.3 DC Characteristics: PIC12F683-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Min -- -- -- D021E -- -- -- D022E D023E -- -- -- -- -- D024E -- -- -- D025E -- -- -- D026E -- -- Typ 0.99 1.2 2.9 1.8 2.7 8.4 58 109 18 28 60 58 85 138 7.0 8.6 10 1.2 0.0029 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD nA nA nA A A A A A A A A A A A A A A A A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current(3) T1OSC Current(3) CVREF Current(3) Comparator Current(3) BOD Current(3) WDT Current(3) Note WDT, BOD, Comparator, VREF and T1OSC disabled DC CHARACTERISTICS Param No. Device Characteristics Power-down Base Current(4)
Sym
D020E IPD
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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15.4 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Sym VIL
Characteristic Input Low Voltage I/O port: with TTL buffer with Schmitt Trigger buffer Ultra Low-Power MCLR, OSC1 (RC mode) OSC1 (XT and LP modes)(1) OSC1 (HS mode)(1)
D030 D030A D031 **TBD D032 D033 D033A VIH D040 D040A D041 TBD D042 D043 D043A D043B D070 D060 D061 D063 VOL D080 D083 VOH D090 D092 IPUR IIL
Vss Vss Vss -- VSS VSS VSS
-- -- -- -- -- -- -- --
0.8 0.15 VDD 0.2 VDD -- 0.2 VDD 0.3 0.3 VDD
V V V -- V V V
4.5V VDD 5.5V Otherwise Entire range
Input High Voltage I/O port: with TTL buffer with Schmitt Trigger buffer Ultra Low-Power MCLR OSC1 (XT and LP modes) OSC1 (HS mode) OSC1 (RC mode) GPIO Weak Pull-up Current Input Leakage Current I/O port MCLR(3) OSC1 Output Low Voltage I/O port OSC2/CLKOUT (RC mode) Output High Voltage I/O port OSC2/CLKOUT (RC mode) VDD - 0.7 VDD - 0.7 -- -- -- -- V V IOH = -3.0 mA, VDD = 4.5V (Ind.) IOH = -1.3 mA, VDD = 4.5V (Ind.) IOH = -1.0 mA, VDD = 4.5V (Ext.) -- -- -- -- 0.6 0.6 V V IOL = 8.5 mA, VDD = 4.5V (Ind.) IOL = 1.6 mA, VDD = 4.5V (Ind.) IOL = 1.2 mA, VDD = 4.5V (Ext.)
(2)
2.0 (0.25 VDD + 0.8) 0.8 VDD -- 0.8 VDD 1.6 0.7 VDD 0.9 VDD 50* -- -- --
-- -- -- -- -- -- -- -- 250 0.1 0.1 0.1
VDD VDD VDD -- VDD VDD VDD VDD 400* 1 5 5
V V V -- V V V V A A A A
4.5V VDD 5.5V Otherwise Entire range
(Note 1) (Note 1) VDD = 5.0V, VPIN = VSS VSS VPIN VDD, Pin at hi-impedance VSS VPIN VDD VSS VPIN VDD, XT, HS and LP oscillator configuration
Legend: TBD = To Be Determined * These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 "Using the Data EEPROM" for additional information.
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15.4 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Ultra Low-Power Wake-up Current Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin -- -- 15* pF In XT, HS and LP modes when external clock is used to drive OSC1 Min -- Typ 200 Max -- Units nA Conditions
DC CHARACTERISTICS Param No. D100
Sym IULP
D101 D120 D120A D121
CIO ED ED VDRW
All I/O pins Data EEPROM Memory Byte Endurance Byte Endurance VDD for Read/Write
-- 100K 10K VMIN
-- 1M 100K --
50* -- -- 5.5
pF E/W -40C TA +85C E/W +85C TA +125C V Using EECON1 to read/write VMIN = Minimum operating voltage
D122 D123 D124
TDEW TRETD TREF
Erase/Write Cycle Time Characteristic Retention Number of Total Erase/Write Cycles before Refresh(4) Program Flash Memory Cell Endurance Cell Endurance VDD for Read VDD for Erase/Write Erase/Write cycle time Characteristic Retention
-- 40 1M
5 -- 10M
6 -- --
ms Year Provided no other specifications are violated E/W -40C TA +85C
D130 D130A D131 D132 D133 D134
EP ED VPR VPEW TPEW TRETD
10K 1K VMIN 4.5 -- 40
100K 10K -- -- 2 --
-- -- 5.5 5.5 2.5 --
E/W -40C TA +85C E/W +85C TA +125C V V ms Year Provided no other specifications are violated VMIN = Minimum operating voltage
Legend: TBD = To Be Determined * These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 "Using the Data EEPROM" for additional information.
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PIC12F683
15.5 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid High-impedance
FIGURE 15-2:
LOAD CONDITIONS
Load Condition 1 VDD/2 Load Condition 2
RL
pin VSS
RL = 464 CL = 50 pF 15 pF
CL
pin VSS
CL
for all pins for OSC2 output
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PIC12F683
15.6 AC Characteristics: PIC12F683 (Industrial, Extended)
EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 15-3:
OSC1 1 2 CLKOUT 3 3 4 4
TABLE 15-1:
EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. Sym FOSC Characteristic External CLKIN Frequency(1) Min DC DC DC DC Oscillator Frequency(1) 5 -- DC 0.1 1 1 TOSC External CLKIN Period(1) 27 50 50 250 Oscillator Period(1) 27 -- 250 250 50 2 3 TCY TosL, TosH Instruction Cycle Time(1) External CLKIN (OSC1) High External CLKIN Low 200 2* 20* 100 * 4 TosR, TosF External CLKIN Rise External CLKIN Fall -- -- -- Typ -- -- -- -- -- 4 -- -- -- -- -- -- -- -- 250 -- -- -- TCY -- -- -- -- -- -- Max 37 4 20 20 37 -- 4 4 20 -- -- -- -- 200 -- -- 10,000 1,000 DC -- -- -- 50* 25* 15* Units kHz MHz MHz MHz kHz MHz MHz MHz MHz s ns ns ns s ns ns ns ns ns s ns ns ns ns ns Conditions LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode INTOSC mode RC Oscillator mode XT Oscillator mode HS Oscillator mode LP Oscillator mode HS Oscillator mode EC Oscillator mode XT Oscillator mode LP Oscillator mode INTOSC mode RC Oscillator mode XT Oscillator mode HS Oscillator mode TCY = 4/FOSC LP oscillator, TOSC L/H duty cycle HS oscillator, TOSC L/H duty cycle XT oscillator, TOSC L/H duty cycle LP oscillator XT oscillator HS oscillator
* These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at `min' values with an external clock applied to OSC1 pin. When an external clock input is used, the `max' cycle time limit is `DC' (no clock) for all devices.
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DS41211B-page 119
PIC12F683
TABLE 15-2: PRECISION INTERNAL OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. F10 Sym FOSC Characteristic Internal Calibrated INTOSC Frequency(1) Freq Min Tolerance 1% 2% 5% -- -- -- Typ 8.00 8.00 8.00 Max -- -- -- Units Conditions
MHz VDD and Temperature (TBD) MHz 2.5V VDD 5.5V 0C TA +85C MHz 2.0V VDD 5.5V -40C TA +85C (Ind.) -40C TA +125C (Ext.) s s s VDD = 2.0V, -40C to +85C VDD = 3.0V, -40C to +85C VDD = 5.0V, -40C to +85C
F14
TIOSCST Oscillator Wake-up from Sleep Start-up Time*
-- -- --
-- -- --
TBD TBD TBD
TBD TBD TBD
Legend: TBD = To Be Determined * These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
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PIC12F683
FIGURE 15-4: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 15 New Value 19 18 22 23 12 16 Q1 Q2 11 Q3
TABLE 15-3:
CLKOUT AND I/O TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Sym Characteristic Min -- -- -- -- -- TOSC + 200 ns 0 -- -- TosH2ioI OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time) 100 0 -- -- 25 TCY Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 10 -- -- Max 200 200 100 100 20 -- -- 150* 300 -- -- 40 40 -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckL OSC1 to CLOUT TosH2ckH OSC1 to CLOUT TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV CLKOUT Rise Time CLKOUT Fall Time CLKOUT to Port Out Valid Port In Valid before CLKOUT Port In Hold after CLKOUT OSC1 (Q1 cycle) to Port Out Valid
TioV2osH Port Input Valid to OSC1 (I/O in setup time) TioR TioF Tinp Trbp Port Output Rise Time Port Output Fall Time INT pin High or Low Time GPIO Change INT High or Low Time
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
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DS41211B-page 121
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FIGURE 15-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O pins 32 30
31 34
FIGURE 15-6:
BROWN-OUT DETECT TIMING AND CHARACTERISTICS
VDD BVDD (Device in Brown-out Detect) (Device not in Brown-out Detect)
35
Reset (due to BOD)
64 ms Time-out(1)
Note 1:
64 ms delay only if PWRTE bit in Configuration Word register is programmed to `0'.
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PIC12F683
TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT DETECT REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. 30 31 32 33* 34 Sym TMCL TWDT TOST TPWRT TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (no prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Detect Voltage Brown-out Detect Pulse Width Brown-out Detect Response Time Brown-out Detect Retriggerable Delay Time Min 2 11 10 10 -- 28* TBD -- Typ -- 18 17 17 1024TOSC 64 TBD -- Max -- 24 25 30 -- 132* TBD 2.0 Units s ms ms ms -- ms ms s Conditions VDD = 5V, -40C to +85C Extended temperature VDD = 5V, -40C to +85C Extended temperature TOSC = OSC1 period VDD = 5V, -40C to +85C Extended Temperature
BVDD 35 36 37 TBOD TR TRD
2.025 100* -- 5
-- -- -- 10
2.175 -- 1 15
V s s s VDD BVDD (D005)
Legend: TBD = To Be Determined * These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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DS41211B-page 123
PIC12F683
FIGURE 15-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 42 41
T1CKI 45 47 TMR0 or TMR1 46 48
TABLE 15-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. 40* 41* 42* Sym Tt0H Tt0L Tt0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous 46* Tt1L T1CKI Low Time Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous 47* Tt1P T1CKI Input Period Synchronous 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 DC 2 TOSC* Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions
45*
Tt1H
T1CKI High Time
-- -- -- -- -- -- --
-- -- -- -- -- -- --
ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
Asynchronous Ft1 48 Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN)
-- -- --
-- 200* 7 TOSC*
ns kHz --
TCKEZtmr1 Delay from External Clock Edge to Timer Increment
* These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC12F683
FIGURE 15-8: CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCP1 (Capture mode)
50 52
51
CCP1 (Compare or PWM mode)
53 Note: Refer to Figure 15-2 for load conditions.
54
TABLE 15-6:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Symbol No. 50* 51* 52* 53* 54* TccL TccH TccP TccR TccF Characteristic CCP1 Input Low Time CCP1 Input High Time CCP1 Input Period CCP1 Output Rise Time CCP1 Output Fall Time No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20 20 0.5 TCY + 20 20 3 TCY + 40 N -- -- Typ Max -- -- -- -- -- 25 25 -- -- -- -- -- 50 45 Units ns ns ns ns ns ns ns N = prescale value (1, 4 or 16) Conditions
* These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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DS41211B-page 125
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TABLE 15-7: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Sym VOS VCM CMRR TRT Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time(1) Min -- 0 +55* -- -- Typ 5.0 -- -- 150 -- Max 10 VDD - 1.5 -- 400* 10* Units mV V db ns s Comments
TMC2COV Comparator Mode Change to Output Valid * Note 1:
These parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD - 1.5V.
TABLE 15-8:
COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Min -- -- -- -- -- -- Typ VDD/24* VDD/32 -- -- 2k* -- Max -- -- 1/4* 1/2* -- 10* Units LSb LSb LSb LSb s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)
Voltage Reference Specifications Sym. Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling * Note 1: Time(1)
These parameters are characterized but not tested. Settling time measured while VRR = 1 and VR<3:0> transitions from `0000' to `1111'.
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PIC12F683
TABLE 15-9: PIC12F683 A/D CONVERTER CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. A01 A02 A03 A04 A05 A06 A07 A10 A20 A20A A25 A30 Sym NR EABS EIL EDL EFS EOFF EGN -- VREF Characteristic Resolution Total Absolute Error*(1) Integral Error Differential Error Full-scale Range Offset Error Gain Error Monotonicity Reference Voltage Min -- -- -- -- 2.2* -- -- -- 2.2 2.5 VSS -- Typ -- -- -- -- -- -- -- guaranteed(2) -- Max 10 1 1 1 5.5* 1 1 -- VDD + 0.3 VDD + 0.3 VREF 10 Units bit LSb VREF = 5.0V LSb VREF = 5.0V LSb No missing codes to 10 bits VREF = 5.0V V LSb VREF = 5.0V LSb VREF = 5.0V -- V VSS VAIN VREF+ 0C TA +125C Absolute limits to ensure 10-bit accuracy Conditions
VAIN ZAIN
Analog Input Voltage Recommended Impedance of Analog Voltage Source VREF Input Current*(3)
-- --
V K
A50
IREF
10
--
1000
A A
--
--
10
During VAIN acquisition. Based on differential of VHOLD to VAIN. During A/D conversion cycle.
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: VREF current is from external VREF or VDD pin, whichever is selected as reference input. 4: When A/D is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the A/D module.
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Preliminary
DS41211B-page 127
PIC12F683
FIGURE 15-9: PIC12F683 A/D CONVERSION TIMING (NORMAL MODE)
1 TCY 131 130 A/D CLK A/D Data ADRES ADIF GO Sample Note 1: 132 Sampling Stopped 9 8 OLD_DATA 7 6 3 2 1 0 NEW_DATA 1 TCY DONE BSF ADCON0, GO 134 Q4
(TOSC/2)(1)
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 15-10: PIC12F683 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. 130 130 Sym TAD TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period Conversion Time (not including Acquisition Time)(1) Acquisition Time 5* Min 1.6 3.0* 3.0* 2.0* 131 TCNV -- Typ -- -- 6.0 4.0 11 Max -- -- 9.0* 6.0* -- Units s s s s TAD Conditions TOSC based, VREF 3.0V TOSC based, VREF full range ADCS<1:0> = 11 (RC mode) At VDD = 2.5V At VDD = 5.0V Set GO bit to new data in A/D Result register
132
TACQ
11.5 --
-- --
s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 4.1 mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to A/D Clock Start
--
TOSC/2
--
--
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Table 9-1 for minimum conditions.
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PIC12F683
FIGURE 15-10: PIC12F683 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO 134 Q4 130 A/D CLK A/D Data ADRES ADIF GO Sample Note 1: 132 Sampling Stopped 9 8 7 6 3 2 1 0 NEW_DATA 1 TCY DONE
(TOSC/2 + TCY)(1)
131
1 TCY
OLD_DATA
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 15-11: PIC12F683 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. 130 Sym TAD Characteristic A/D Internal RC Oscillator Period Conversion Time (not including Acquisition Time)(1) Acquisition Time Min Typ Max Units s s TAD Conditions ADCS<1:0> = 11 (RC mode) At VDD = 2.5V At VDD = 5.0V
3.0* 2.0* --
6.0 4.0 11
9.0* 6.0* --
131
Tcnv
132
TACQ
(2) 5*
11.5 --
-- --
s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 4.1 mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to A/D Clock Start
--
TOSC/2 + TCY
--
--
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Table 9-1 for minimum conditions.
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Preliminary
DS41211B-page 129
PIC12F683
NOTES:
DS41211B-page 130
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PIC12F683
16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Graphs and Tables are not available at this time.
2004 Microchip Technology Inc.
DS41211B-page 131
PIC12F683
NOTES:
DS41211B-page 132
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PIC12F683
17.0
17.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (Skinny DIP) Example
XXXXXXXX XXXXXNNN YYWW
12F683-I /P017 0415
8-Lead SOIC XXXXXXXX XXXXYYWW NNN
Example 12F683-E /SN0415 017
8-Lead DFN-S
Example
XXXXXXX XXXXXXX XXYYWW NNN
12F683 -E/MF 0415 017
Legend:
XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
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DS41211B-page 133
PIC12F683
17.2 Package Details
The following sections give the technical details of the packages.
8-Lead Plastic Dual In-line (P) - 300 mil Body (PDIP)
E1
D 2 n 1 E
A
A2
c
L A1
eB
B1 p B
Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB
MIN
INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10
MAX
MIN
.140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5
.170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15
MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018
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8-Lead Plastic Small Outline (SN) - Narrow, 150 mil Body (SOIC)
E E1
p
D 2 B n 1
h 45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0
INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12
MAX
MIN
.069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15
MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057
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PIC12F683
8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) - Punch Singulated
E E1
n
B
p
L R D1 D D2
1
2
EXPOSED METAL PADS
PIN 1 INDEX
E2
TOP VIEW
A2
A3
BOTTOM VIEW
A
A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Length Molded Package Length Exposed Pad Length Overall Width Molded Package Width Exposed Pad Width Lead Width Lead Length Tie Bar Width Mold Draft Angle Top
Units Dimension Limits n p A A2 A1 A3 E E1 E2 D D1 D2 B L R
MIN
INCHES NOM 8 .050 BSC .033 .026 .0004 .008 REF. .194 BSC .184 BSC .158 .236 BSC .226 BSC .091 .016 .024 .014
MAX
MIN
.000
.039 .031 .002
.152
.163
.085 .014 .020
.097 .019 .030 12
MILLIMETERS* NOM 8 1.27 BSC 0.85 0.65 0.00 0.01 0.20 REF. 4.92 BSC 4.67 BSC 3.85 4.00 5.99 BSC 5.74 BSC 2.16 2.31 0.40 0.35 0.60 0.50 .356
MAX
1.00 0.80 0.05
4.15
2.46 0.47 0.75 12
*Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: Pending
Drawing No. C04-113
DS41211B-page 136
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2004 Microchip Technology Inc.
PIC12F683
APPENDIX A:
Revision A
This is a new data sheet.
DATA SHEET REVISION HISTORY
APPENDIX B:
MIGRATING FROM OTHER PICmicro(R) DEVICES
This discusses some of the issues in migrating from other PICmicro devices to the PIC12F6XX family of devices.
Revision B
Rewrites of the Oscillator and Special Features of the CPU sections. General corrections to Figures and formatting.
B.1
PIC12F675 to PIC12F683
FEATURE COMPARISON
PIC12F675 20 MHz 1024 64 10-bit 128 1/1 8 Y GP0/1/2/4/5 PIC12F683 20 MHz 2048 128 10-bit 256 2/1 8 Y GP0/1/2/4/5, MCLR 1 Y Y Y Y 32 kHz-8 MHz Y Feature
TABLE B-1:
Max Operating Speed Max Program Memory (Words) SRAM (Bytes) A/D Resolution Data EEPROM (Bytes) Timers (8/16-bit) Oscillator Modes Brown-out Detect Internal Pull-ups Interrupt-on-change Comparators CCP Ultra Low-Power Wake-up Extended WDT Software Control Option of WDT/BOD INTOSC Frequencies Clock Switching
GP0/1/2/3/4/5 GP0/1/2/3/4/5 1 N N N N 4 MHz N
Note:
This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device.
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DS41211B-page 137
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NOTES:
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INDEX
A
A/D ...................................................................................... 55 Acquisition Requirements ........................................... 61 Associated Registers .................................................. 63 Calculating Acquisition Time....................................... 61 Channel Selection....................................................... 55 Configuration and Operation....................................... 55 Configuring.................................................................. 60 Configuring Interrupt ................................................... 60 Conversion Clock........................................................ 55 Conversion Output ...................................................... 57 Conversion Requirements ........................................ 128 Conversion Requirements (Sleep Mode).................. 129 Converter Characteristics ......................................... 127 Effects of a Reset........................................................ 63 Internal Sampling Switch (RSS) Impedance................ 61 Operation During Sleep .............................................. 62 Reference Voltage (VREF)........................................... 55 Source Impedance...................................................... 61 Starting a Conversion ................................................. 57 Absolute Maximum Ratings .............................................. 109 AC Characteristics Industrial and Extended ............................................ 119 Analog Input Connection Considerations............................ 48 Analog-to-Digital Converter. See A/D. Assembler MPASM Assembler................................................... 103 MPLAB C30.............................................................. 104 Calibration Bits.................................................................... 77 Capture Module. See Capture/Compare/PWM (CCP) Capture/Compare/PWM (CCP) .......................................... 69 Associated Registers.................................................. 74 Associated Registers with Capture, Compare and Timer1.......................................... 71 Capture Mode............................................................. 70 Prescaler ............................................................ 70 CCP1 Pin Configuration ............................................. 70 Compare Special Trigger Output of CCP1 ......................... 71 Compare Mode........................................................... 71 CCP1 Pin Configuration ..................................... 71 Software Interrupt Mode ..................................... 71 Special Event Trigger ......................................... 71 Timer1 Mode Selection....................................... 71 PWM Mode................................................................. 72 Duty Cycle .......................................................... 73 Example Frequencies/Resolutions ..................... 73 PWM Period ....................................................... 72 Setup .................................................................. 73 TMR2 to PR2 Match ........................................... 45 Special Event Trigger and A/D Conversions .............. 71 Timer Resources ........................................................ 69 Capture/Compare/PWM (CCP) Requirements ................. 125 CCP. See Capture/Compare/PWM (CCP). CLKOUT and I/O Timing Requirements ........................... 121 Clock Sources..................................................................... 19 Associated Registers.................................................. 29 Code Examples A/D Conversion .......................................................... 60 Changing Between Capture Prescalers ..................... 70 Changing Prescaler from Timer0 to WDT .................. 40 Changing Prescaler from WDT to Timer0 .................. 40 Data EEPROM Read.................................................. 67 Data EEPROM Write .................................................. 67 Indirect Addressing..................................................... 17 Initializing GPIO.......................................................... 31 Saving Status and W Registers in RAM ..................... 88 Ultra Low-Power Wake-up Initialization...................... 34 Write Verify ................................................................. 67 Code Protection .................................................................. 92 Comparator......................................................................... 47 Associated Registers.................................................. 54 Configurations ............................................................ 49 COUT as T1 Gate................................................. 42, 51 Effects of a Reset ....................................................... 53 I/O Operating Modes .................................................. 49 Interrupts .................................................................... 51 Operation.................................................................... 48 Operation During Sleep .............................................. 53 Outputs ....................................................................... 51 Response Time .......................................................... 53 Specifications ........................................................... 126 Synchronizing COUT w/Timer1 .................................. 51 Comparator Voltage Reference (CVREF)............................ 52 Accuracy/Error............................................................ 52 Associated Registers.................................................. 54 Configuring ................................................................. 52 Effects of a Reset ....................................................... 53 Response Time .......................................................... 53 Specifications ........................................................... 126
B
Block Diagrams A/D .............................................................................. 55 Analog Input Model ............................................... 48, 61 Capture Mode Operation ............................................ 70 Ceramic Resonator Operation .................................... 21 Comparator Output ..................................................... 50 Comparator Voltage Reference (CVREF) .................... 52 Compare ..................................................................... 71 Fail-Safe Clock Monitor (FSCM) ................................. 27 GP0 Pin....................................................................... 34 GP1 Pin....................................................................... 35 GP2 Pin....................................................................... 35 GP3 Pin....................................................................... 36 GP4 Pin....................................................................... 36 GP5 Pin....................................................................... 37 In-Circuit Serial Programming Connection.................. 93 Interrupt Logic ............................................................. 86 On-Chip Reset Circuit ................................................. 78 PIC12F683.................................................................... 5 PIC12F683 Clock Source ........................................... 19 Recommended MCLR Circuit ..................................... 79 Simplified PWM Mode................................................. 72 Timer1......................................................................... 41 Timer2......................................................................... 46 TMR0/WDT Prescaler................................................. 39 Watchdog Timer (WDT) .............................................. 89 Brown-out Detect (BOD) ..................................................... 80 Associated Registers .................................................. 81 Calibration................................................................... 80
C
C Compilers MPLAB C17 .............................................................. 104 MPLAB C18 .............................................................. 104
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 139
PIC12F683
Compare Module. See Capture/Compare/PWM (CCP) Configuration Bits................................................................ 76 CPU Features ..................................................................... 75
I
ID Locations........................................................................ 92 In-Circuit Debugger............................................................. 93 In-Circuit Serial Programming (ICSP)................................. 92 Indirect Addressing, INDF and FSR Registers ................... 17 Instruction Format............................................................... 95 Instruction Set..................................................................... 95 ADDLW....................................................................... 97 ADDWF....................................................................... 97 ANDLW....................................................................... 97 ANDWF....................................................................... 97 BCF ............................................................................ 97 BSF............................................................................. 97 BTFSC ........................................................................ 97 BTFSS ........................................................................ 97 CALL........................................................................... 98 CLRF .......................................................................... 98 CLRW ......................................................................... 98 CLRWDT .................................................................... 98 COMF ......................................................................... 98 DECF .......................................................................... 98 DECFSZ ..................................................................... 99 GOTO ......................................................................... 99 INCF ........................................................................... 99 INCFSZ....................................................................... 99 IORLW ...................................................................... 100 IORWF...................................................................... 100 MOVF ......................................................................... 99 MOVLW .................................................................... 100 MOVWF .................................................................... 100 NOP .......................................................................... 100 RETFIE ..................................................................... 100 RETLW ..................................................................... 101 RETURN................................................................... 101 RLF ........................................................................... 101 RRF .......................................................................... 101 SLEEP ...................................................................... 102 SUBLW ..................................................................... 102 SUBWF..................................................................... 102 SWAPF ..................................................................... 102 XORLW .................................................................... 102 XORWF .................................................................... 102 Summary Table .......................................................... 96 Internal Sampling Switch (RSS) Impedance........................ 61 Interrupts............................................................................. 85 A/D.............................................................................. 60 Associated Registers .................................................. 87 Capture ....................................................................... 70 Comparator................................................................. 51 Compare ..................................................................... 71 Context Saving ........................................................... 88 Data EEPROM Memory Write .................................... 66 GP2/INT...................................................................... 85 GPIO Interrupt-on-change .......................................... 86 Interrupt-on-change .................................................... 33 TMR0 .......................................................................... 86 TMR2 to PR2 Match (PWM) ....................................... 45
D
Data EEPROM Memory Associated Registers .................................................. 68 Code Protection .................................................... 65, 68 Data Memory Organization ................................................... 7 Map of the PIC12F683 .................................................. 8 DC and AC Characteristics Graphs and Tables........................... 131 DC Characteristics Extended ................................................................... 114 Industrial ................................................................... 112 Industrial and Extended .................................... 111, 116 Demonstration Boards PICDEM 1 ................................................................. 106 PICDEM 17 ............................................................... 107 PICDEM 18R ............................................................ 107 PICDEM 2 Plus ......................................................... 106 PICDEM 3 ................................................................. 106 PICDEM 4 ................................................................. 106 PICDEM LIN ............................................................. 107 PICDEM USB............................................................ 107 PICDEM.net Internet/Ethernet .................................. 106 Development Support ....................................................... 103 Device Overview ................................................................... 5
E
EECON1 and EECON2 (EEPROM Control) Registers....... 66 EEPROM Data Memory Avoiding Spurious Write.............................................. 68 Reading....................................................................... 67 Write Verify ................................................................. 67 Writing ......................................................................... 67 Electrical Specifications .................................................... 109 Errata .................................................................................... 3 Evaluation and Programming Tools .................................. 107 External Clock Timing Requirements................................ 119
F
Fail-Safe Clock Monitor....................................................... 27 Fail-Safe Condition Clearing ....................................... 27 Reset or Wake-up from Sleep..................................... 28 Firmware Instructions.......................................................... 95 Fuses. See Configuration Bits.
G
General Purpose Register File.............................................. 7 GPIO ................................................................................... 31 Additional Pin Functions ............................................. 31 Interrupt-on-change ............................................ 33 Ultra Low-Power Wake-up .................................. 33 Weak Pull-up....................................................... 31 and the TRISIO Registers ........................................... 31 Associated Registers .................................................. 38 GP0 ............................................................................. 34 GP1 ............................................................................. 35 GP2 ............................................................................. 35 GP3 ............................................................................. 36 GP4 ............................................................................. 36 GP5 ............................................................................. 37 Pin Descriptions and Diagrams................................... 34
L
Load Conditions................................................................ 118
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2004 Microchip Technology Inc.
PIC12F683
M
MCLR .................................................................................. 79 Internal ........................................................................ 79 Memory Organization Data EEPROM Memory.............................................. 65 Migrating from other PICmicro Devices ............................ 137 MPLAB ASM30 Assembler, Linker, Librarian ................... 104 MPLAB ICD 2 In-Circuit Debugger ................................... 105 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ................................................... 105 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator .................................................... 105 MPLAB Integrated Development Environment Software.................................................................... 103 MPLAB PM3 Device Programmer .................................... 105 MPLINK Object Linker/MPLIB Object Librarian ................ 104 CMCON1 (Comparator Control 1) .............................. 50 CONFIG (Configuration Word) ................................... 76 EEADR (EEPROM Address) ...................................... 65 EECON1 (EEPROM Control) ..................................... 66 EEDAT (EEPROM Data) ............................................ 65 GPIO (General Purpose I/O) ...................................... 31 INTCON (Interrupt Control) ........................................ 13 IOC (Interrupt-on-change GPIO) ................................ 33 OPTION_REG (Option) .............................................. 12 OSCCON (Oscillator Control)..................................... 28 PCON (Power Control) ............................................... 16 PIE1 (Peripheral Interrupt Enable 1) .......................... 14 PIR1 (Peripheral Interrupt Request 1) ........................ 15 Reset Values .............................................................. 83 Reset Values (Special Registers)............................... 84 Status ......................................................................... 11 T1CON (Timer1 Control) ............................................ 43 T2CON (Timer2 Control) ............................................ 45 TRISIO (GPIO Tri-State) ............................................ 32 VRCON (Voltage Reference Control) ......................... 53 WDTCON (Watchdog Timer Control) ......................... 90 WPU (Weak Pull-up) .................................................. 32 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Detect Requirements ............. 123 Resets ................................................................................ 78 Brown-out Detect (BOD)............................................. 78 MCLR Reset, Normal Operation................................. 78 MCLR Reset, Sleep.................................................... 78 Power-on Reset (POR)............................................... 78 WDT Reset, Normal Operation................................... 78 WDT Reset, Sleep...................................................... 78 Revision History................................................................ 137
O
Opcode Field Descriptions .................................................. 95 Oscillator Switching Fail-Safe Clock Monitor............................................... 27 Two-Speed Clock Start-up.......................................... 25
P
Packaging ......................................................................... 133 Details ....................................................................... 134 Marking ..................................................................... 133 PCL and PCLATH ............................................................... 17 Computed GOTO........................................................ 17 Stack ........................................................................... 17 PCON (Power Control) Register ......................................... 81 PICkit 1 Flash Starter Kit................................................... 107 PICSTART Plus Development Programmer ..................... 106 Pin Diagram .......................................................................... 2 Pinout Descriptions PIC12F683.................................................................... 6 PORTC Associated Registers .................................................. 29 Power-Down Mode (Sleep) ................................................. 91 Wake-up...................................................................... 91 Using Interrupts .................................................. 91 Power-On Reset (POR) ...................................................... 79 Power-up Timer (PWRT) .................................................... 79 Precision Internal Oscillator Parameters........................... 120 Prescaler Shared WDT/Timer0 ................................................... 40 Switching Prescaler Assignment................................. 40 PRO MATE II Universal Device Programmer ................... 105 Product Identification ........................................................ 145 Program Memory Organization ............................................. 7 Map and Stack for the PIC12F683................................ 7 Programming, Device Instructions ...................................... 95 Pulse Width Modulation. See Capture/Compare/PWM, PWM Mode.
S
Software Simulator (MPLAB SIM) .................................... 104 Software Simulator (MPLAB SIM30) ................................ 104 Special Function Registers ................................................... 8
T
Time-out Sequence ............................................................ 81 Timer0 ................................................................................ 39 Associated Registers.................................................. 40 External Clock ............................................................ 40 Interrupt ...................................................................... 39 Operation.................................................................... 39 T0CKI ......................................................................... 40 Timer0 and Timer1 External Clock Requirements............ 124 Timer1 ................................................................................ 41 Associated Registers.................................................. 44 Asynchronous Counter Mode ..................................... 44 Reading and Writing ........................................... 44 Gate Inverting Gate ..................................................... 42 Selecting Source ................................................ 42 Interrupt Interrupt .............................................................. 42 Modes of Operations .................................................. 42 Operation During Sleep .............................................. 44 Oscillator..................................................................... 44 Prescaler .................................................................... 42 Timer1 Gate Selecting Source ................................................ 51 Synchronizing COUT w/Timer1 .......................... 51 TMR1H Register......................................................... 41 TMR1L Register ......................................................... 41
R
Read-Modify-Write Operations ........................................... 95 Registers ADCON0 (A/D Control) ............................................... 58 ANSEL (Analog Select)............................................... 59 CALIB (Calibration Word) ........................................... 77 CCP1CON (CCP Control 1)........................................ 69 CCPR1H ..................................................................... 69 CCPR1L...................................................................... 69 CMCON0 (Comparator Control 0) .............................. 47
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 141
PIC12F683
Timer2 ................................................................................. 45 Associated Registers .................................................. 46 Interrupt....................................................................... 46 Operation .................................................................... 45 Postscaler ................................................................... 45 PR2 Register............................................................... 45 Prescaler ..................................................................... 45 TMR2 Register ............................................................ 45 TMR2 to PR2 Match Interrupt ..................................... 45 Timing Diagrams A/D Conversion (Normal Mode) ................................ 128 A/D Conversion (Sleep Mode) .................................. 129 Brown-out Detect (BOD) ........................................... 122 Brown-out Detect Situations ....................................... 80 Capture/Compare/PWM (CCP)................................. 125 CLKOUT and I/O....................................................... 121 External Clock ........................................................... 119 Fail-Safe Clock Monitor (FSCM) ................................. 27 INT Pin Interrupt.......................................................... 87 PWM Output ............................................................... 72 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ................................................ 122 Single Comparator ...................................................... 48 Time-out Sequence on Power-up (Delayed MCLR) ... 82 Time-out Sequence on Power-up (MCLR with VDD)... 82 Timer0 and Timer1 External Clock ........................... 124 Timer1 Incrementing Edge.......................................... 42 Two Speed Start-up .................................................... 26 Wake-up from Sleep Through Interrupt ...................... 92 Timing Parameter Symbology........................................... 118 Two-Speed Clock Start-up Mode ........................................ 25
U
Ultra Low-Power Wake-up.................................................. 33
V
Voltage Reference. See Comparator Voltage Reference (CVREF). VREF. See A/D Reference Voltage.
W
Watchdog Timer (WDT)...................................................... 89 Associated Registers .................................................. 90 Control ........................................................................ 89 Oscillator..................................................................... 89 WWW, On-Line Support ....................................................... 3
DS41211B-page 142
Preliminary
2004 Microchip Technology Inc.
PIC12F683
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site.
SYSTEMS INFORMATION AND UPGRADE HOT LINE
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada and 1-480-792-7302 for the rest of the world. 042003
Connecting to the Microchip Internet Web Site
The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 143
PIC12F683
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC12F683 Questions: 1. What are the best features of this document? Y N Literature Number: DS41211B FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41211B-page 144
Preliminary
2004 Microchip Technology Inc.
PIC12F683
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device PIC12F683: Standard VDD range PIC12F683T: (Tape and Reel) PIC12F683-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 PIC12F683-I/SO = Industrial Temp., SOIC package, 20 MHz
Temperature Range
I E
= =
-40C to +85C -40C to +125C
Package
P SN MF
= = =
PDIP SOIC (Gull wing, 150 mil body) DFN-S
Pattern
3-Digit Pattern Code for QTP (blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 145
WORLDWIDE SALES AND SERVICE
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02/17/04
DS41211B-page 146
Preliminary
2004 Microchip Technology Inc.

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